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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
lib/Target/AMDGPU/SIISelLowering.cpp 6771 MachineFunction &MF = DAG.getMachineFunction();
6782 DAG.getTargetConstant(Tgt->getZExtValue(), DL, MVT::i8), // tgt
6783 DAG.getTargetConstant(En->getZExtValue(), DL, MVT::i8), // en
6788 DAG.getTargetConstant(0, DL, MVT::i1), // compr
6789 DAG.getTargetConstant(VM->getZExtValue(), DL, MVT::i1)
6794 return DAG.getNode(Opc, DL, Op->getVTList(), Ops);
6804 SDValue Undef = DAG.getUNDEF(MVT::f32);
6807 DAG.getTargetConstant(Tgt->getZExtValue(), DL, MVT::i8), // tgt
6808 DAG.getTargetConstant(En->getZExtValue(), DL, MVT::i8), // en
6809 DAG.getNode(ISD::BITCAST, DL, MVT::f32, Src0),
6810 DAG.getNode(ISD::BITCAST, DL, MVT::f32, Src1),
6813 DAG.getTargetConstant(1, DL, MVT::i1), // compr
6814 DAG.getTargetConstant(VM->getZExtValue(), DL, MVT::i1)
6819 return DAG.getNode(Opc, DL, Op->getVTList(), Ops);
6826 return SDValue(DAG.getMachineNode(AMDGPU::WAVE_BARRIER, DL, MVT::Other,
6835 VData = handleD16VData(VData, DAG);
6851 DAG.getTargetConstant(Dfmt | (Nfmt << 4), DL, MVT::i32), // format
6852 DAG.getTargetConstant(Glc | (Slc << 1), DL, MVT::i32), // cachepolicy
6853 DAG.getTargetConstant(IdxEn, DL, MVT::i1), // idexen
6858 return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
6866 VData = handleD16VData(VData, DAG);
6867 auto Offsets = splitBufferOffsets(Op.getOperand(5), DAG);
6878 DAG.getTargetConstant(1, DL, MVT::i1), // idexen
6883 return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
6891 VData = handleD16VData(VData, DAG);
6892 auto Offsets = splitBufferOffsets(Op.getOperand(4), DAG);
6897 DAG.getConstant(0, DL, MVT::i32), // vindex
6903 DAG.getTargetConstant(0, DL, MVT::i1), // idexen
6908 return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
6917 VData = handleD16VData(VData, DAG);
6931 DAG.getTargetConstant(Glc | (Slc << 1), DL, MVT::i32), // cachepolicy
6932 DAG.getTargetConstant(IdxEn, DL, MVT::i1), // idxen
6934 unsigned Offset = setBufferOffsets(Op.getOperand(5), DAG, &Ops[4]);
6947 return handleByteShortBufferStores(DAG, VDataType, DL, Ops, M);
6949 return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
6963 VData = handleD16VData(VData, DAG);
6967 DAG.getNode(ISD::BITCAST, DL,
6968 getEquivalentMemType(*DAG.getContext(), VDataVT), VData);
6971 auto Offsets = splitBufferOffsets(Op.getOperand(4), DAG);
6976 DAG.getConstant(0, DL, MVT::i32), // vindex
6981 DAG.getTargetConstant(0, DL, MVT::i1), // idxen
6991 return handleByteShortBufferStores(DAG, VDataVT, DL, Ops, M);
6993 return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
7008 VData = handleD16VData(VData, DAG);
7012 DAG.getNode(ISD::BITCAST, DL,
7013 getEquivalentMemType(*DAG.getContext(), VDataVT), VData);
7016 auto Offsets = splitBufferOffsets(Op.getOperand(5), DAG);
7026 DAG.getTargetConstant(1, DL, MVT::i1), // idxen
7038 return handleByteShortBufferStores(DAG, VDataType, DL, Ops, M);
7040 return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
7057 DAG.getTargetConstant(Slc << 1, DL, MVT::i32), // cachepolicy
7058 DAG.getTargetConstant(IdxEn, DL, MVT::i1), // idxen
7060 unsigned Offset = setBufferOffsets(Op.getOperand(5), DAG, &Ops[4]);
7071 return DAG.getMemIntrinsicNode(Opcode, DL, Op->getVTList(), Ops, VT,
7087 return DAG.getMemIntrinsicNode(Opcode, DL, Op->getVTList(), Ops, VT,
7092 return SDValue(DAG.getMachineNode(AMDGPU::SI_END_CF, DL, MVT::Other,
7098 return lowerImage(Op, ImageDimIntr, DAG);