reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
3584 MachineFunction *MF = BB->getParent(); 3594 return BB; 3600 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 3631 BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0) 3634 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1) 3637 BuildMI(*BB, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), Dest.getReg()) 3643 return BB; 3646 BuildMI(*BB, MI.getIterator(), MI.getDebugLoc(), 3650 return BB; 3654 BuildMI(*BB, &*BB->begin(), MI.getDebugLoc(), TII->get(AMDGPU::S_MOV_B64), 3654 BuildMI(*BB, &*BB->begin(), MI.getDebugLoc(), TII->get(AMDGPU::S_MOV_B64), 3658 return BB; 3662 BuildMI(*BB, &*BB->begin(), MI.getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), 3662 BuildMI(*BB, &*BB->begin(), MI.getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), 3666 return BB; 3676 MachineInstr *FirstMI = &*BB->begin(); 3683 for (auto I = BB->begin(); I != &MI; I++) { 3689 FirstMI = &*++BB->begin(); 3692 BB->insert(FirstMI, &*I); 3704 BuildMI(*BB, FirstMI, DebugLoc(), TII->get(AMDGPU::S_BFE_U32), CountReg) 3707 BuildMI(*BB, FirstMI, DebugLoc(), 3712 BuildMI(*BB, FirstMI, DebugLoc(), TII->get(AMDGPU::S_CMP_EQ_U32)) 3715 BuildMI(*BB, FirstMI, DebugLoc(), 3720 return BB; 3727 BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_MOV_B32)) 3731 return BB; 3738 return emitIndirectSrc(MI, *BB, *getSubtarget()); 3744 return emitIndirectDst(MI, *BB, *getSubtarget()); 3747 return splitKillBlock(MI, BB); 3749 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 3764 BuildMI(*BB, MI, DL, TII->get(AMDGPU::COPY), SrcCondCopy) 3766 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstLo) 3772 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstHi) 3779 BuildMI(*BB, MI, DL, TII->get(AMDGPU::REG_SEQUENCE), Dst) 3785 return BB; 3790 MachineInstr *Br = BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_CBRANCH_SCC1)) 3794 return BB; 3807 return BB; 3816 MIB = BuildMI(*BB, MI, DL, TII->get(AMDGPU::SI_CALL), ReturnAddrReg); 3823 return BB; 3838 auto I = BuildMI(*BB, MI, DL, TII->get(Opc), MI.getOperand(0).getReg()); 3852 return BB; 3863 return BB; 3866 return emitGWSMemViolTestLoop(MI, BB); 3868 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);