reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
591 TRI = ST.getRegisterInfo(); 614 std::tie(SrcRC, DstRC) = getCopyRegClasses(MI, *TRI, *MRI); 621 if (DstReg == AMDGPU::M0 && TRI->hasVectorRegisters(SrcRC)) { 634 if (isVGPRToSGPRCopy(SrcRC, DstRC, *TRI)) { 653 } else if (isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)) { 654 tryChangeVGPRtoSGPRinCopy(MI, TRI, TII); 664 if (TRI->hasVectorRegisters(TII->getOpRegClass(MI, 0)) || 665 !hasVectorOperands(MI, TRI)) { 666 foldVGPRCopyIntoRegSequence(MI, TRI, TII, *MRI); 679 if (TRI->isSGPRClass(DstRC) && 680 (TRI->hasVectorRegisters(Src0RC) || 681 TRI->hasVectorRegisters(Src1RC))) { 707 if ((Src0.isReg() && TRI->isSGPRReg(*MRI, Src0.getReg()) && 709 (Src1.isReg() && TRI->isSGPRReg(*MRI, Src1.getReg()) && 753 hoistAndMergeSGPRInits(AMDGPU::M0, *MRI, TRI, *MDT, TII); 771 TRI->isAGPR(*MRI, UseMI->getOperand(0).getReg())) || 772 TRI->isAGPR(*MRI, Use.getReg()); 776 !TRI->isSGPRReg(*MRI, UseMI->getOperand(0).getReg())) { 787 if (!TRI->isSGPRReg(*MRI, Use.getReg()) && 795 if (!TRI->isSGPRClass(OpRC) && OpRC != &AMDGPU::VS_32RegClass && 804 if (AllAGPRUses && numVGPRUses && !TRI->hasAGPRs(RC0)) { 806 MRI->setRegClass(PHIRes, TRI->getEquivalentAGPRClass(RC0)); 813 if (TRI->isVectorRegister(*MRI, InputReg)) { 817 TRI->getRegClassForReg(*MRI, SrcReg); 818 if (TRI->isSGPRClass(RC)) 825 TRI->isVectorRegister(*MRI, Def->getOperand(1).getReg())) { 831 if ((!TRI->isVectorRegister(*MRI, PHIRes) &&