reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
590 MRI = &MF.getRegInfo(); 614 std::tie(SrcRC, DstRC) = getCopyRegClasses(MI, *TRI, *MRI); 623 = MRI->createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); 641 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); 666 foldVGPRCopyIntoRegSequence(MI, TRI, TII, *MRI); 676 DstRC = MRI->getRegClass(MI.getOperand(0).getReg()); 677 Src0RC = MRI->getRegClass(MI.getOperand(1).getReg()); 678 Src1RC = MRI->getRegClass(MI.getOperand(2).getReg()); 707 if ((Src0.isReg() && TRI->isSGPRReg(*MRI, Src0.getReg()) && 709 (Src1.isReg() && TRI->isSGPRReg(*MRI, Src1.getReg()) && 719 MachineInstr *DefMI = MRI->getVRegDef(MO->getReg()); 753 hoistAndMergeSGPRInits(AMDGPU::M0, *MRI, TRI, *MDT, TII); 768 for (const auto &Use : MRI->use_operands(Reg)) { 771 TRI->isAGPR(*MRI, UseMI->getOperand(0).getReg())) || 772 TRI->isAGPR(*MRI, Use.getReg()); 776 !TRI->isSGPRReg(*MRI, UseMI->getOperand(0).getReg())) { 786 const TargetRegisterClass *UseRC = MRI->getRegClass(Use.getReg()); 787 if (!TRI->isSGPRReg(*MRI, Use.getReg()) && 803 const TargetRegisterClass *RC0 = MRI->getRegClass(PHIRes); 806 MRI->setRegClass(PHIRes, TRI->getEquivalentAGPRClass(RC0)); 812 MachineInstr *Def = MRI->getVRegDef(InputReg); 813 if (TRI->isVectorRegister(*MRI, InputReg)) { 817 TRI->getRegClassForReg(*MRI, SrcReg); 825 TRI->isVectorRegister(*MRI, Def->getOperand(1).getReg())) { 831 if ((!TRI->isVectorRegister(*MRI, PHIRes) &&