reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
604 switch (MI.getOpcode()) { 611 Register DstReg = MI.getOperand(0).getReg(); 614 std::tie(SrcRC, DstRC) = getCopyRegClasses(MI, *TRI, *MRI); 625 BuildMI(MBB, MI, MI.getDebugLoc(), 625 BuildMI(MBB, MI, MI.getDebugLoc(), 627 .add(MI.getOperand(1)); 628 MI.getOperand(1).setReg(TmpReg); 635 Register SrcReg = MI.getOperand(1).getReg(); 637 TII->moveToVALU(MI, MDT); 646 if (isSafeToFoldImmIntoCopy(&MI, DefMI, TII, SMovOp, Imm)) { 647 MI.getOperand(1).ChangeToImmediate(Imm); 648 MI.addImplicitDefUseOperands(MF); 649 MI.setDesc(TII->get(SMovOp)); 652 TII->moveToVALU(MI, MDT); 654 tryChangeVGPRtoSGPRinCopy(MI, TRI, TII); 660 processPHINode(MI); 664 if (TRI->hasVectorRegisters(TII->getOpRegClass(MI, 0)) || 665 !hasVectorOperands(MI, TRI)) { 666 foldVGPRCopyIntoRegSequence(MI, TRI, TII, *MRI); 670 LLVM_DEBUG(dbgs() << "Fixing REG_SEQUENCE: " << MI); 672 TII->moveToVALU(MI, MDT); 676 DstRC = MRI->getRegClass(MI.getOperand(0).getReg()); 677 Src0RC = MRI->getRegClass(MI.getOperand(1).getReg()); 678 Src1RC = MRI->getRegClass(MI.getOperand(2).getReg()); 682 LLVM_DEBUG(dbgs() << " Fixing INSERT_SUBREG: " << MI); 683 TII->moveToVALU(MI, MDT); 690 if (ST.getConstantBusLimit(MI.getOpcode()) != 1) 700 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0); 702 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src1); 703 MachineOperand &Src0 = MI.getOperand(Src0Idx); 704 MachineOperand &Src1 = MI.getOperand(Src1Idx); 740 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), 740 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), 740 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),