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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc15744 static const MCOperandInfo OperandInfo402[] = { { AMDGPU::AReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_128RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15746 static const MCOperandInfo OperandInfo404[] = { { AMDGPU::AReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_512RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15747 static const MCOperandInfo OperandInfo405[] = { { AMDGPU::AReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_512RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15749 static const MCOperandInfo OperandInfo407[] = { { AMDGPU::AReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_128RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15751 static const MCOperandInfo OperandInfo409[] = { { AMDGPU::AReg_1024RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_1024RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15752 static const MCOperandInfo OperandInfo410[] = { { AMDGPU::AReg_1024RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_1024RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp 1474 case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
1748 case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
1788 case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp 525 case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp 241 case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
lib/Target/AMDGPU/SIInstrInfo.cpp 2336 if (!isInlineConstant(*ImmOp, AMDGPU::OPERAND_REG_INLINE_AC_INT32))
2848 case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
3259 case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h 585 case AMDGPU::OPERAND_REG_INLINE_AC_INT32: