reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
6398 return (Imm >= DppCtrl::QUAD_PERM_FIRST && Imm <= DppCtrl::QUAD_PERM_LAST) || 6398 return (Imm >= DppCtrl::QUAD_PERM_FIRST && Imm <= DppCtrl::QUAD_PERM_LAST) || 6399 (Imm >= DppCtrl::ROW_SHL_FIRST && Imm <= DppCtrl::ROW_SHL_LAST) || 6399 (Imm >= DppCtrl::ROW_SHL_FIRST && Imm <= DppCtrl::ROW_SHL_LAST) || 6400 (Imm >= DppCtrl::ROW_SHR_FIRST && Imm <= DppCtrl::ROW_SHR_LAST) || 6400 (Imm >= DppCtrl::ROW_SHR_FIRST && Imm <= DppCtrl::ROW_SHR_LAST) || 6401 (Imm >= DppCtrl::ROW_ROR_FIRST && Imm <= DppCtrl::ROW_ROR_LAST) || 6401 (Imm >= DppCtrl::ROW_ROR_FIRST && Imm <= DppCtrl::ROW_ROR_LAST) || 6402 (Imm == DppCtrl::WAVE_SHL1) || 6403 (Imm == DppCtrl::WAVE_ROL1) || 6404 (Imm == DppCtrl::WAVE_SHR1) || 6405 (Imm == DppCtrl::WAVE_ROR1) || 6406 (Imm == DppCtrl::ROW_MIRROR) || 6407 (Imm == DppCtrl::ROW_HALF_MIRROR) || 6408 (Imm == DppCtrl::BCAST15) || 6409 (Imm == DppCtrl::BCAST31) || 6410 (Imm >= DppCtrl::ROW_SHARE_FIRST && Imm <= DppCtrl::ROW_SHARE_LAST) || 6410 (Imm >= DppCtrl::ROW_SHARE_FIRST && Imm <= DppCtrl::ROW_SHARE_LAST) || 6411 (Imm >= DppCtrl::ROW_XMASK_FIRST && Imm <= DppCtrl::ROW_XMASK_LAST); 6411 (Imm >= DppCtrl::ROW_XMASK_FIRST && Imm <= DppCtrl::ROW_XMASK_LAST); 6557 Int = DppCtrl::ROW_MIRROR; 6560 Int = DppCtrl::ROW_HALF_MIRROR; 6623 Int |= DppCtrl::ROW_SHL0; 6625 Int |= DppCtrl::ROW_SHR0; 6627 Int |= DppCtrl::ROW_ROR0; 6629 Int = DppCtrl::WAVE_SHL1; 6631 Int = DppCtrl::WAVE_ROL1; 6633 Int = DppCtrl::WAVE_SHR1; 6635 Int = DppCtrl::WAVE_ROR1; 6638 Int = DppCtrl::BCAST15; 6640 Int = DppCtrl::BCAST31; 6645 Int |= DppCtrl::ROW_SHARE_FIRST; 6647 Int |= DppCtrl::ROW_XMASK_FIRST;lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
701 if (Imm <= DppCtrl::QUAD_PERM_LAST) { 707 } else if ((Imm >= DppCtrl::ROW_SHL_FIRST) && 708 (Imm <= DppCtrl::ROW_SHL_LAST)) { 711 } else if ((Imm >= DppCtrl::ROW_SHR_FIRST) && 712 (Imm <= DppCtrl::ROW_SHR_LAST)) { 715 } else if ((Imm >= DppCtrl::ROW_ROR_FIRST) && 716 (Imm <= DppCtrl::ROW_ROR_LAST)) { 719 } else if (Imm == DppCtrl::WAVE_SHL1) { 725 } else if (Imm == DppCtrl::WAVE_ROL1) { 731 } else if (Imm == DppCtrl::WAVE_SHR1) { 737 } else if (Imm == DppCtrl::WAVE_ROR1) { 743 } else if (Imm == DppCtrl::ROW_MIRROR) { 745 } else if (Imm == DppCtrl::ROW_HALF_MIRROR) { 747 } else if (Imm == DppCtrl::BCAST15) { 753 } else if (Imm == DppCtrl::BCAST31) { 759 } else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) && 760 (Imm <= DppCtrl::ROW_SHARE_LAST)) { 767 } else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) && 768 (Imm <= DppCtrl::ROW_XMASK_LAST)) {lib/Target/AMDGPU/SIInstrInfo.cpp
3694 if (DC == DppCtrl::DPP_UNUSED1 || DC == DppCtrl::DPP_UNUSED2 || 3694 if (DC == DppCtrl::DPP_UNUSED1 || DC == DppCtrl::DPP_UNUSED2 || 3695 DC == DppCtrl::DPP_UNUSED3 || DC > DppCtrl::DPP_LAST || 3695 DC == DppCtrl::DPP_UNUSED3 || DC > DppCtrl::DPP_LAST || 3696 (DC >= DppCtrl::DPP_UNUSED4_FIRST && DC <= DppCtrl::DPP_UNUSED4_LAST) || 3696 (DC >= DppCtrl::DPP_UNUSED4_FIRST && DC <= DppCtrl::DPP_UNUSED4_LAST) || 3697 (DC >= DppCtrl::DPP_UNUSED5_FIRST && DC <= DppCtrl::DPP_UNUSED5_LAST) || 3697 (DC >= DppCtrl::DPP_UNUSED5_FIRST && DC <= DppCtrl::DPP_UNUSED5_LAST) || 3698 (DC >= DppCtrl::DPP_UNUSED6_FIRST && DC <= DppCtrl::DPP_UNUSED6_LAST) || 3698 (DC >= DppCtrl::DPP_UNUSED6_FIRST && DC <= DppCtrl::DPP_UNUSED6_LAST) || 3699 (DC >= DppCtrl::DPP_UNUSED7_FIRST && DC <= DppCtrl::DPP_UNUSED7_LAST) || 3699 (DC >= DppCtrl::DPP_UNUSED7_FIRST && DC <= DppCtrl::DPP_UNUSED7_LAST) || 3700 (DC >= DppCtrl::DPP_UNUSED8_FIRST && DC <= DppCtrl::DPP_UNUSED8_LAST)) { 3700 (DC >= DppCtrl::DPP_UNUSED8_FIRST && DC <= DppCtrl::DPP_UNUSED8_LAST)) { 3704 if (DC >= DppCtrl::WAVE_SHL1 && DC <= DppCtrl::WAVE_ROR1 && 3704 if (DC >= DppCtrl::WAVE_SHL1 && DC <= DppCtrl::WAVE_ROR1 && 3710 if (DC >= DppCtrl::BCAST15 && DC <= DppCtrl::BCAST31 && 3710 if (DC >= DppCtrl::BCAST15 && DC <= DppCtrl::BCAST31 && 3716 if (DC >= DppCtrl::ROW_SHARE_FIRST && DC <= DppCtrl::ROW_XMASK_LAST && 3716 if (DC >= DppCtrl::ROW_SHARE_FIRST && DC <= DppCtrl::ROW_XMASK_LAST &&