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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
lib/Target/AMDGPU/R600ISelLowering.cpp 474 MachineFunction &MF = DAG.getMachineFunction();
477 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
478 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
479 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
480 case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG);
482 case ISD::SRL_PARTS: return LowerSRXParts(Op, DAG);
483 case ISD::UADDO: return LowerUADDSUBO(Op, DAG, ISD::ADD, AMDGPUISD::CARRY);
484 case ISD::USUBO: return LowerUADDSUBO(Op, DAG, ISD::SUB, AMDGPUISD::BORROW);
486 case ISD::FSIN: return LowerTrig(Op, DAG);
487 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
488 case ISD::STORE: return LowerSTORE(Op, DAG);
490 SDValue Result = LowerLOAD(Op, DAG);
497 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
498 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
499 case ISD::FrameIndex: return lowerFrameIndex(Op, DAG);
512 DAG.getConstant(0, DL, MVT::i32), // SWZ_X
513 DAG.getConstant(1, DL, MVT::i32), // SWZ_Y
514 DAG.getConstant(2, DL, MVT::i32), // SWZ_Z
515 DAG.getConstant(3, DL, MVT::i32) // SWZ_W
517 return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, Op.getValueType(), Args);
547 DAG.getConstant(TextureOp, DL, MVT::i32),
549 DAG.getConstant(0, DL, MVT::i32),
550 DAG.getConstant(1, DL, MVT::i32),
551 DAG.getConstant(2, DL, MVT::i32),
552 DAG.getConstant(3, DL, MVT::i32),
556 DAG.getConstant(0, DL, MVT::i32),
557 DAG.getConstant(1, DL, MVT::i32),
558 DAG.getConstant(2, DL, MVT::i32),
559 DAG.getConstant(3, DL, MVT::i32),
567 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs);
571 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
572 DAG.getConstant(0, DL, MVT::i32)),
573 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
574 DAG.getConstant(0, DL, MVT::i32)),
575 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
576 DAG.getConstant(1, DL, MVT::i32)),
577 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
578 DAG.getConstant(1, DL, MVT::i32)),
579 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
580 DAG.getConstant(2, DL, MVT::i32)),
581 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
582 DAG.getConstant(2, DL, MVT::i32)),
583 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
584 DAG.getConstant(3, DL, MVT::i32)),
585 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
586 DAG.getConstant(3, DL, MVT::i32))
588 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args);
592 MVT PtrVT = getPointerTy(DAG.getDataLayout(), AMDGPUAS::PARAM_I_ADDRESS);
594 return DAG.getConstant(ByteOffset, DL, PtrVT);
597 return LowerImplicitParameter(DAG, VT, DL, 0);
599 return LowerImplicitParameter(DAG, VT, DL, 1);
601 return LowerImplicitParameter(DAG, VT, DL, 2);
603 return LowerImplicitParameter(DAG, VT, DL, 3);
605 return LowerImplicitParameter(DAG, VT, DL, 4);
607 return LowerImplicitParameter(DAG, VT, DL, 5);
609 return LowerImplicitParameter(DAG, VT, DL, 6);
611 return LowerImplicitParameter(DAG, VT, DL, 7);
613 return LowerImplicitParameter(DAG, VT, DL, 8);
616 return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass,
619 return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass,
622 return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass,
625 return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass,
628 return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass,
631 return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass,
635 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
638 return DAG.getNode(AMDGPUISD::RSQ_CLAMP, DL, VT, Op.getOperand(1));