reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
234 OS << llvm::printReg(Reg, TRI); 238 OS << "<unassigned> " << llvm::printReg(Reg, TRI); 240 OS << llvm::printReg(Reg, TRI) << '(' 241 << llvm::printReg(VRM->getPhys(Reg), TRI) << ')'; 243 OS << ':' << TRI->getSubRegIndexName(SubReg); 280 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 281 unsigned Size = TRI->getRegSizeInBits(*RC); 283 Reg = TRI->getSubReg(Reg, AMDGPU::sub0); 285 if (TRI->hasVGPRs(RC)) { 290 Reg = TRI->getEncodingValue(Reg) / 2; 304 Reg = TRI->getSubReg(Reg, SubReg); 307 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 308 unsigned Size = TRI->getRegSizeInBits(*RC) / 32; 310 Reg = TRI->getSubReg(Reg, AMDGPU::sub0); 312 if (TRI->hasVGPRs(RC)) { 328 Reg = TRI->getEncodingValue(Reg) / 2; 368 if (TRI->hasAGPRs(TRI->getRegClassForReg(*MRI, R))) 368 if (TRI->hasAGPRs(TRI->getRegClassForReg(*MRI, R))) 374 unsigned LM = TRI->getSubRegIndexLaneMask(Op.getSubReg()).getAsInteger(); 414 if (Def->modifiesRegister(Reg1, TRI)) 416 if (Def->modifiesRegister(Reg2, TRI)) 441 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysReg); 442 if (TRI->hasVGPRs(RC)) 445 unsigned Size = TRI->getRegSizeInBits(*RC); 447 PhysReg = TRI->getSubReg(PhysReg, AMDGPU::sub0); 498 unsigned LM = TRI->getSubRegIndexLaneMask(SubReg).getAsInteger(); 599 if (TRI->isSubRegisterEq(Reg, MaxReg)) 606 if (TRI->isSubRegisterEq(Reg, CSRegs[I]) && 714 return C.MI->readsRegister(Reg, TRI); 733 TRI = ST->getRegisterInfo(); 749 TRI->getEncodingValue(AMDGPU::SGPR_NULL) / 2 + 1);