reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
168 OrigMI.getDebugLoc(), TII->get(DPPOp)); 171 auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst); 192 if (auto *Mod0 = TII->getNamedOperand(OrigMI, 204 auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0); 206 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src0)) { 215 if (auto *Mod1 = TII->getNamedOperand(OrigMI, 227 if (auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1)) { 228 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src1)) { 237 if (auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2)) { 238 if (!TII->getNamedOperand(*DPPInst.getInstr(), AMDGPU::OpName::src2) || 239 !TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src2)) { 247 DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl)); 248 DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask)); 249 DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask)); 320 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); 342 auto *Imm = TII->getNamedOperand(MI, OpndName); 354 auto *DstOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst); 367 auto *RowMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask); 369 auto *BankMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask); 374 auto *BCZOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bound_ctrl); 378 auto *OldOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::old); 379 auto *SrcOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0); 438 TII->get(AMDGPU::IMPLICIT_DEF), CombOldVGPR.Reg); 487 if (TII->isVOP3(OrigOp)) { 488 if (!TII->hasVALU32BitEncoding(OrigOp)) { 501 } else if (!TII->isVOP1(OrigOp) && !TII->isVOP2(OrigOp)) { 501 } else if (!TII->isVOP1(OrigOp) && !TII->isVOP2(OrigOp)) { 507 if (Use == TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0)) { 514 Use == TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1)) { 518 if (TII->commuteInstruction(*NewMI)) { 560 TII = ST.getInstrInfo(); 572 auto Split = TII->expandMovDPP64(MI);