reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
 3710       if (!isUInt<sizeof(KD.group_segment_fixed_size) * CHAR_BIT>(Val))
 3712       KD.group_segment_fixed_size = Val;
 3714       if (!isUInt<sizeof(KD.private_segment_fixed_size) * CHAR_BIT>(Val))
 3716       KD.private_segment_fixed_size = Val;
 3720                        Val, ValRange);
 3721       if (Val)
 3725                        KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR, Val,
 3727       if (Val)
 3731                        KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR, Val,
 3733       if (Val)
 3738                        Val, ValRange);
 3739       if (Val)
 3743                        KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID, Val,
 3745       if (Val)
 3749                        KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT, Val,
 3751       if (Val)
 3756                        Val, ValRange);
 3757       if (Val)
 3763       EnableWavefrontSize32 = Val;
 3766                        Val, ValRange);
 3770           COMPUTE_PGM_RSRC2_ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET, Val,
 3774                        COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X, Val,
 3778                        COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y, Val,
 3782                        COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z, Val,
 3786                        COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO, Val,
 3790                        COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID, Val,
 3794       NextFreeVGPR = Val;
 3797       NextFreeSGPR = Val;
 3799       if (!isUInt<1>(Val))
 3801       ReserveVCC = Val;
 3806       if (!isUInt<1>(Val))
 3808       ReserveFlatScr = Val;
 3813       if (!isUInt<1>(Val))
 3815       ReserveXNACK = Val;
 3818                        COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32, Val, ValRange);
 3821                        COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64, Val, ValRange);
 3824                        COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32, Val, ValRange);
 3827                        COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64, Val,
 3831                        COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP, Val, ValRange);
 3834                        Val, ValRange);
 3839       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_FP16_OVFL, Val,
 3845       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_WGP_MODE, Val,
 3851       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_MEM_ORDERED, Val,
 3857       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_FWD_PROGRESS, Val,
 3862           COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION, Val,
 3867                        Val, ValRange);
 3871           COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO, Val,
 3876                        Val, ValRange);
 3880                        Val, ValRange);
 3884                        Val, ValRange);
 3888                        Val, ValRange);