reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
 6557     Int = DppCtrl::ROW_MIRROR;
 6560     Int = DppCtrl::ROW_HALF_MIRROR;
 6598       if (getParser().parseAbsoluteExpression(Int) || !(0 <= Int && Int <=3))
 6598       if (getParser().parseAbsoluteExpression(Int) || !(0 <= Int && Int <=3))
 6598       if (getParser().parseAbsoluteExpression(Int) || !(0 <= Int && Int <=3))
 6610         Int += (Temp << shift);
 6619       if (getParser().parseAbsoluteExpression(Int))
 6622       if (Prefix == "row_shl" && 1 <= Int && Int <= 15) {
 6622       if (Prefix == "row_shl" && 1 <= Int && Int <= 15) {
 6623         Int |= DppCtrl::ROW_SHL0;
 6624       } else if (Prefix == "row_shr" && 1 <= Int && Int <= 15) {
 6624       } else if (Prefix == "row_shr" && 1 <= Int && Int <= 15) {
 6625         Int |= DppCtrl::ROW_SHR0;
 6626       } else if (Prefix == "row_ror" && 1 <= Int && Int <= 15) {
 6626       } else if (Prefix == "row_ror" && 1 <= Int && Int <= 15) {
 6627         Int |= DppCtrl::ROW_ROR0;
 6628       } else if (Prefix == "wave_shl" && 1 == Int) {
 6629         Int = DppCtrl::WAVE_SHL1;
 6630       } else if (Prefix == "wave_rol" && 1 == Int) {
 6631         Int = DppCtrl::WAVE_ROL1;
 6632       } else if (Prefix == "wave_shr" && 1 == Int) {
 6633         Int = DppCtrl::WAVE_SHR1;
 6634       } else if (Prefix == "wave_ror" && 1 == Int) {
 6635         Int = DppCtrl::WAVE_ROR1;
 6637         if (Int == 15) {
 6638           Int = DppCtrl::BCAST15;
 6639         } else if (Int == 31) {
 6640           Int = DppCtrl::BCAST31;
 6644       } else if (Prefix == "row_share" && 0 <= Int && Int <= 15) {
 6644       } else if (Prefix == "row_share" && 0 <= Int && Int <= 15) {
 6645         Int |= DppCtrl::ROW_SHARE_FIRST;
 6646       } else if (Prefix == "row_xmask" && 0 <= Int && Int <= 15) {
 6646       } else if (Prefix == "row_xmask" && 0 <= Int && Int <= 15) {
 6647         Int |= DppCtrl::ROW_XMASK_FIRST;
 6654   Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, AMDGPUOperand::ImmTyDppCtrl));