reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
6682 const MCInstrDesc &Desc = MII.get(Inst.getOpcode()); 6684 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1); 6689 auto TiedTo = Desc.getOperandConstraint(Inst.getNumOperands(), 6692 assert((unsigned)TiedTo < Inst.getNumOperands()); 6694 Inst.addOperand(Inst.getOperand(TiedTo)); 6694 Inst.addOperand(Inst.getOperand(TiedTo)); 6706 Op.addImmOperands(Inst, 1); 6707 } else if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) { 6708 Op.addRegWithFPInputModsOperands(Inst, 2); 6712 Op.addRegOperands(Inst, 1); 6717 if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) { 6718 Op.addRegWithFPInputModsOperands(Inst, 2); 6720 Op.addImmOperands(Inst, 1); 6732 Inst.addOperand(MCOperand::createImm(Fi? DPP8_FI_1 : DPP8_FI_0)); 6734 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf); 6735 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf); 6736 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl); 6737 if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::fi) != -1) { 6738 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppFi);