reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
1022 MFI->initializeBaseYamlFields(YamlMFI); 1045 if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) || 1046 parseRegister(YamlMFI.ScratchWaveOffsetReg, MFI->ScratchWaveOffsetReg) || 1047 parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) || 1048 parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg)) 1051 if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG && 1052 !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) { 1056 if (MFI->ScratchWaveOffsetReg != AMDGPU::SCRATCH_WAVE_OFFSET_REG && 1057 !AMDGPU::SGPR_32RegClass.contains(MFI->ScratchWaveOffsetReg)) { 1061 if (MFI->FrameOffsetReg != AMDGPU::FP_REG && 1062 !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) { 1066 if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG && 1067 !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) { 1094 MFI->NumUserSGPRs += UserSGPRs; 1095 MFI->NumSystemSGPRs += SystemSGPRs; 1102 MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) || 1104 AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr, 1107 MFI->ArgInfo.QueuePtr, 2, 0) || 1110 MFI->ArgInfo.KernargSegmentPtr, 2, 0) || 1112 AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID, 1116 MFI->ArgInfo.FlatScratchInit, 2, 0) || 1119 MFI->ArgInfo.PrivateSegmentSize, 0, 0) || 1121 AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX, 1124 AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY, 1127 AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ, 1131 MFI->ArgInfo.WorkGroupInfo, 0, 1) || 1134 MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) || 1137 MFI->ArgInfo.ImplicitArgPtr, 0, 0) || 1140 MFI->ArgInfo.ImplicitBufferPtr, 2, 0) || 1143 MFI->ArgInfo.WorkItemIDX, 0, 0) || 1146 MFI->ArgInfo.WorkItemIDY, 0, 0) || 1149 MFI->ArgInfo.WorkItemIDZ, 0, 0))) 1152 MFI->Mode.IEEE = YamlMFI.Mode.IEEE; 1153 MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;