reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
687 LLT ResTy = MRI.getType(Def.getReg()); 688 const RegisterBank *DefBank = getRegBank(Def.getReg(), MRI, *TRI); 691 Register PhiReg = MRI.createGenericVirtualRegister(ResTy); 694 MRI.setRegBank(PhiReg, *DefBank); 695 MRI.setRegBank(InitReg, *DefBank); 699 Register SaveExecReg = MRI.createVirtualRegister(WaveRC); 700 Register InitSaveExecReg = MRI.createVirtualRegister(WaveRC); 706 Register PhiExec = MRI.createVirtualRegister(WaveRC); 707 Register NewExec = MRI.createVirtualRegister(WaveRC); 770 LLT OpTy = MRI.getType(Op.getReg()); 777 = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); 778 MRI.setType(CurrentLaneOpReg, OpTy); 780 constrainGenericRegister(Op.getReg(), AMDGPU::VGPR_32RegClass, MRI); 786 Register NewCondReg = MRI.createVirtualRegister(WaveRC); 799 Register AndReg = MRI.createVirtualRegister(WaveRC); 836 Register CurrentLaneOpRegLo = MRI.createGenericVirtualRegister(S32); 837 Register CurrentLaneOpRegHi = MRI.createGenericVirtualRegister(S32); 839 MRI.setRegClass(UnmergePiece, &AMDGPU::VReg_64RegClass); 840 MRI.setRegClass(CurrentLaneOpRegLo, &AMDGPU::SReg_32_XM0RegClass); 841 MRI.setRegClass(CurrentLaneOpRegHi, &AMDGPU::SReg_32_XM0RegClass); 858 MRI.setRegClass(CurrentLaneOpReg, &AMDGPU::SReg_64_XEXECRegClass); 870 CurrentLaneOpReg = MRI.createGenericVirtualRegister(S32); 871 MRI.setRegClass(UnmergePiece, &AMDGPU::VGPR_32RegClass); 872 MRI.setRegClass(CurrentLaneOpReg, &AMDGPU::SReg_32_XM0RegClass); 881 Register NewCondReg = MRI.createVirtualRegister(WaveRC); 892 Register AndReg = MRI.createVirtualRegister(WaveRC); 913 MRI.setRegBank(Op.getReg(), getRegBank(AMDGPU::SGPRRegBankID)); 926 MRI.setSimpleHint(NewExec, CondReg);