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References

lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
 1334     LLT DstTy = MRI.getType(DstReg);
 1361       setRegsToType(MRI, Src1Regs, HalfTy);
 1367       setRegsToType(MRI, Src2Regs, HalfTy);
 1369     setRegsToType(MRI, DefRegs, HalfTy);
 1374     MRI.setRegBank(DstReg, getRegBank(AMDGPU::VGPRRegBankID));
 1384     LLT DstTy = MRI.getType(DstReg);
 1411       setRegsToType(MRI, Src0Regs, HalfTy);
 1416       setRegsToType(MRI, Src1Regs, HalfTy);
 1418     setRegsToType(MRI, DefRegs, HalfTy);
 1430     MRI.setRegBank(DstReg, getRegBank(AMDGPU::VGPRRegBankID));
 1438     LLT DstTy = MRI.getType(DstReg);
 1442     const RegisterBank *DstBank = getRegBank(DstReg, MRI, *TRI);
 1449     ApplyRegBankMapping ApplySALU(MRI, &AMDGPU::SGPRRegBank);
 1463     const RegisterBank *DstBank = getRegBank(DstReg, MRI, *TRI);
 1469     ApplyRegBankMapping ApplySALU(MRI, &AMDGPU::SGPRRegBank);
 1474     LLT Ty = MRI.getType(DstReg);
 1496     LLT SrcTy = MRI.getType(SrcReg);
 1500     const RegisterBank *SrcBank = getRegBank(SrcReg, MRI, *TRI);
 1503     LLT DstTy = MRI.getType(DstReg);
 1522         MRI.setRegBank(ShiftAmt.getReg(0), *SrcBank);
 1529       MRI.setRegBank(DstReg, *SrcBank);
 1553       MRI.setRegBank(True.getReg(0), *DstBank);
 1554       MRI.setRegBank(False.getReg(0), *DstBank);
 1555       MRI.setRegBank(DstReg, *DstBank);
 1562         MRI.setRegBank(Sel.getReg(0), *DstBank);
 1584     MRI.setRegBank(DstReg, *SrcBank);
 1585     MRI.setRegBank(Ext.getReg(0), *SrcBank);
 1586     MRI.setRegBank(ShiftAmt.getReg(0), *SrcBank);
 1587     MRI.setRegBank(Shl.getReg(0), *SrcBank);
 1594     LLT DstTy = MRI.getType(DstReg);
 1602     const RegisterBank *DstBank = getRegBank(DstReg, MRI, *TRI);
 1612     const RegisterBank *BankLo = getRegBank(Lo, MRI, *TRI);
 1613     const RegisterBank *BankHi = getRegBank(Hi, MRI, *TRI);
 1620       MRI.setRegBank(ZextLo, *BankLo);
 1623       MRI.setRegBank(ZextHi, *BankHi);
 1626       MRI.setRegBank(ShiftAmt.getReg(0), *BankHi);
 1629       MRI.setRegBank(ShiftHi, *BankHi);
 1632       MRI.setRegBank(MaskLo, *BankLo);
 1635       MRI.setRegBank(ShiftAmt.getReg(0), *BankHi);
 1638       MRI.setRegBank(ShiftHi, *BankHi);
 1641       MRI.setRegBank(ZextLo, *BankLo);
 1645     MRI.setRegBank(Or.getReg(0), *DstBank);
 1658       executeInWaterfallLoop(MI, MRI, { 2 });
 1665     LLT DstTy = MRI.getType(DstReg);
 1670     LLT SrcTy = MRI.getType(SrcReg);
 1694     const RegisterBank *SrcBank = getRegBank(SrcReg, MRI, *TRI);
 1695     MRI.setRegBank(DstReg, *DstMapping.BreakDown[0].RegBank);
 1696     MRI.setRegBank(CastSrc.getReg(0), *SrcBank);
 1697     MRI.setRegBank(One.getReg(0), AMDGPU::SGPRRegBank);
 1698     MRI.setRegBank(IdxLo.getReg(0), AMDGPU::SGPRRegBank);
 1699     MRI.setRegBank(IdxHi.getReg(0), AMDGPU::SGPRRegBank);
 1702     if (!collectWaterfallOperands(OpsToWaterfall, MI, MRI, { 2 })) {
 1712                            OpsToWaterfall, MRI);
 1724       executeInWaterfallLoop(MI, MRI, { 3 });
 1732     LLT SrcTy = MRI.getType(SrcReg);
 1733     LLT InsTy = MRI.getType(InsReg);
 1759     const RegisterBank *DstBank = getRegBank(DstReg, MRI, *TRI);
 1760     const RegisterBank *SrcBank = getRegBank(SrcReg, MRI, *TRI);
 1761     const RegisterBank *InsSrcBank = getRegBank(InsReg, MRI, *TRI);
 1763     MRI.setRegBank(InsReg, *InsSrcBank);
 1764     MRI.setRegBank(CastSrc.getReg(0), *SrcBank);
 1765     MRI.setRegBank(InsLo.getReg(0), *DstBank);
 1766     MRI.setRegBank(InsHi.getReg(0), *DstBank);
 1767     MRI.setRegBank(One.getReg(0), AMDGPU::SGPRRegBank);
 1768     MRI.setRegBank(IdxLo.getReg(0), AMDGPU::SGPRRegBank);
 1769     MRI.setRegBank(IdxHi.getReg(0), AMDGPU::SGPRRegBank);
 1773     if (!collectWaterfallOperands(OpsToWaterfall, MI, MRI, { 3 })) {
 1782                            OpsToWaterfall, MRI);
 1789       executeInWaterfallLoop(MI, MRI, { 2, 3 });
 1800       constrainOpWithReadfirstlane(MI, MRI, 3); // Index
 1809       constrainOpWithReadfirstlane(MI, MRI, 2); // Source value
 1810       constrainOpWithReadfirstlane(MI, MRI, 3); // Index
 1822       executeInWaterfallLoop(MI, MRI, { 2 });
 1830       constrainOpWithReadfirstlane(MI, MRI, 2); // M0
 1838       constrainOpWithReadfirstlane(MI, MRI, 2); // M0
 1845       constrainOpWithReadfirstlane(MI, MRI, 1); // M0
 1851       constrainOpWithReadfirstlane(MI, MRI, 2); // M0
 1861       executeInWaterfallLoop(MI, MRI, {2, 4});
 1869       executeInWaterfallLoop(MI, MRI, {2, 5});
 1879           applyMappingImage(MI, OpdMapper, MRI, RSrcIntrin->RsrcArg);
 1892     if (applyMappingWideLoad(MI, OpdMapper, MRI))