reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  341   const MachineFunction &MF = *MI.getParent()->getParent();
  346   switch (MI.getOpcode()) {
  348     unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
  357       return addMappingFromTable<1>(MI, MRI, {{ 0 }}, Table);
  370     return addMappingFromTable<1>(MI, MRI, {{ 0 }}, Table);
  375     unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
  446     unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
  447     LLT PtrTy = MRI.getType(MI.getOperand(1).getReg());
  450     LLT LoadTy = MRI.getType(MI.getOperand(0).getReg());
  453         isInstrUniformNonExtLoadAlign4(MI)) {
  479     unsigned Size = getSizeInBits(MI.getOperand(2).getReg(), MRI, *TRI);
  515     unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
  549     return addMappingFromTable<3>(MI, MRI, RegSrcOpIdx, makeArrayRef(Table));
  555     unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
  577     assert(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() == 1);
  593     return getInstrAlternativeMappingsIntrinsic(MI, MRI);
  595     return getInstrAlternativeMappingsIntrinsicWSideEffects(MI, MRI);
  599   return RegisterBankInfo::getInstrAlternativeMappings(MI);