reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
1329 unsigned Opc = MI.getOpcode(); 1333 Register DstReg = MI.getOperand(0).getReg(); 1351 MachineIRBuilder B(MI); 1353 Src0Regs.push_back(MI.getOperand(1).getReg()); 1359 split64BitValueForMapping(B, Src1Regs, HalfTy, MI.getOperand(2).getReg()); 1365 split64BitValueForMapping(B, Src2Regs, HalfTy, MI.getOperand(3).getReg()); 1375 MI.eraseFromParent(); 1383 Register DstReg = MI.getOperand(0).getReg(); 1406 MachineIRBuilder B(MI); 1409 split64BitValueForMapping(B, Src0Regs, HalfTy, MI.getOperand(1).getReg()); 1414 split64BitValueForMapping(B, Src1Regs, HalfTy, MI.getOperand(2).getReg()); 1431 MI.eraseFromParent(); 1437 Register DstReg = MI.getOperand(0).getReg(); 1447 MachineFunction *MF = MI.getParent()->getParent(); 1448 MachineIRBuilder B(MI); 1453 if (Helper.widenScalar(MI, 0, LLT::scalar(32)) != 1462 Register DstReg = MI.getOperand(0).getReg(); 1467 MachineFunction *MF = MI.getParent()->getParent(); 1468 MachineIRBuilder B(MI); 1480 if (Helper.widenScalar(MI, 0, S32) != LegalizerHelper::Legalized) 1484 if (Helper.lower(MI, 0, S32) != LegalizerHelper::Legalized) 1487 if (Helper.lower(MI, 0, Ty) != LegalizerHelper::Legalized) 1495 Register SrcReg = MI.getOperand(1).getReg(); 1499 MachineIRBuilder B(MI); 1502 Register DstReg = MI.getOperand(0).getReg(); 1530 MI.eraseFromParent(); 1568 MI.eraseFromParent(); 1579 if (MI.getOpcode() == AMDGPU::G_SEXT) 1588 MI.eraseFromParent(); 1593 Register DstReg = MI.getOperand(0).getReg(); 1598 assert(MI.getNumOperands() == 3 && OpdMapper.getVRegs(0).empty()); 1606 MachineIRBuilder B(MI); 1608 Register Lo = MI.getOperand(1).getReg(); 1609 Register Hi = MI.getOperand(2).getReg(); 1648 MI.eraseFromParent(); 1658 executeInWaterfallLoop(MI, MRI, { 2 }); 1662 Register DstReg = MI.getOperand(0).getReg(); 1663 Register SrcReg = MI.getOperand(1).getReg(); 1664 Register IdxReg = MI.getOperand(2).getReg(); 1674 MachineIRBuilder B(MI); 1682 MachineInstrSpan Span(MachineBasicBlock::iterator(&MI), &B.getMBB()); 1702 if (!collectWaterfallOperands(OpsToWaterfall, MI, MRI, { 2 })) { 1703 MI.eraseFromParent(); 1710 MI.eraseFromParent(); 1724 executeInWaterfallLoop(MI, MRI, { 3 }); 1728 Register DstReg = MI.getOperand(0).getReg(); 1729 Register SrcReg = MI.getOperand(1).getReg(); 1730 Register InsReg = MI.getOperand(2).getReg(); 1731 Register IdxReg = MI.getOperand(3).getReg(); 1741 MachineIRBuilder B(MI); 1749 MachineInstrSpan Span(MachineBasicBlock::iterator(&MI), &B.getMBB()); 1773 if (!collectWaterfallOperands(OpsToWaterfall, MI, MRI, { 3 })) { 1774 MI.eraseFromParent(); 1779 MI.eraseFromParent(); 1786 switch (MI.getIntrinsicID()) { 1789 executeInWaterfallLoop(MI, MRI, { 2, 3 }); 1800 constrainOpWithReadfirstlane(MI, MRI, 3); // Index 1809 constrainOpWithReadfirstlane(MI, MRI, 2); // Source value 1810 constrainOpWithReadfirstlane(MI, MRI, 3); // Index 1819 auto IntrID = MI.getIntrinsicID(); 1822 executeInWaterfallLoop(MI, MRI, { 2 }); 1830 constrainOpWithReadfirstlane(MI, MRI, 2); // M0 1838 constrainOpWithReadfirstlane(MI, MRI, 2); // M0 1845 constrainOpWithReadfirstlane(MI, MRI, 1); // M0 1851 constrainOpWithReadfirstlane(MI, MRI, 2); // M0 1861 executeInWaterfallLoop(MI, MRI, {2, 4}); 1869 executeInWaterfallLoop(MI, MRI, {2, 5}); 1879 applyMappingImage(MI, OpdMapper, MRI, RSrcIntrin->RsrcArg); 1892 if (applyMappingWideLoad(MI, OpdMapper, MRI))