reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
68 MRI = &MF.getRegInfo(); 122 if (isVCC(DstReg, *MRI)) { 125 = TRI.getConstrainedRegClassForOperand(Dst, *MRI); 128 return RBI.constrainGenericRegister(DstReg, *RC, *MRI); 131 if (!isVCC(SrcReg, *MRI)) { 133 if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), *MRI)) 140 if (!MRI->getRegClassOrNull(SrcReg)) 141 MRI->setRegClass(SrcReg, TRI.getConstrainedRegClassForOperand(Src, *MRI)); 141 MRI->setRegClass(SrcReg, TRI.getConstrainedRegClassForOperand(Src, *MRI)); 147 TRI.getConstrainedRegClassForOperand(Dst, *MRI); 148 if (RC && !RBI.constrainGenericRegister(DstReg, *RC, *MRI)) 159 TRI.getConstrainedRegClassForOperand(Src, *MRI); 160 if (SrcRC && !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI)) 172 TRI.getConstrainedRegClassForOperand(MO, *MRI); 175 RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI); 182 const LLT DefTy = MRI->getType(DefReg); 187 MRI->getRegClassOrRegBank(DefReg); 203 DefRC = TRI.getRegClassForTypeOnBank(DefTy, RB, *MRI); 211 return RBI.constrainGenericRegister(DefReg, *DefRC, *MRI); 221 Register DstReg = MRI->createVirtualRegister(&SubRC); 267 unsigned Size = RBI.getSizeInBits(DstReg, *MRI, TRI); 269 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); 280 if (Src0.isUndef() && !MRI->getRegClassOrNull(Src0.getReg())) 281 MRI->setRegClass(Src0.getReg(), RC); 282 if (Src1.isUndef() && !MRI->getRegClassOrNull(Src1.getReg())) 283 MRI->setRegClass(Src1.getReg(), RC); 285 return RBI.constrainGenericRegister(DstReg, *RC, *MRI); 304 unsigned Size = RBI.getSizeInBits(DstReg, *MRI, TRI); 305 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); 330 Register UnusedCarry = MRI->createVirtualRegister(TRI.getWaveMaskRegClass()); 353 Register DstLo = MRI->createVirtualRegister(&HalfRC); 354 Register DstHi = MRI->createVirtualRegister(&HalfRC); 365 Register CarryReg = MRI->createVirtualRegister(CarryRC); 372 .addDef(MRI->createVirtualRegister(CarryRC), RegState::Dead) 389 if (!RBI.constrainGenericRegister(DstReg, RC, *MRI)) 451 TRI.getConstrainedRegClassForOperand(MO, *MRI); 454 RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI); 463 LLT DstTy = MRI->getType(DstReg); 464 LLT SrcTy = MRI->getType(MI.getOperand(1).getReg()); 471 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); 474 TRI.getRegClassForSizeOnBank(DstSize, *DstBank, *MRI); 487 = TRI.getConstrainedRegClassForOperand(Src, *MRI); 488 if (SrcRC && !RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI)) 492 if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) 507 LLT DstTy = MRI->getType(DstReg0); 508 LLT SrcTy = MRI->getType(SrcReg); 513 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI); 516 TRI.getRegClassForSizeOnBank(SrcSize, *SrcBank, *MRI); 517 if (!SrcRC || !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI)) 532 TRI.getConstrainedRegClassForOperand(Dst, *MRI); 533 if (DstRC && !RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI)) 550 const TargetRegisterClass *RC = TRI.getConstrainedRegClassForOperand(MO, *MRI); 551 if ((!RC && !MRI->getRegBankOrNull(MO.getReg())) || 552 (RC && RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI))) { 566 LLT Src1Ty = MRI->getType(Src1Reg); 568 unsigned DstSize = MRI->getType(DstReg).getSizeInBits(); 579 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); 581 TRI.getRegClassForSizeOnBank(DstSize, *DstBank, *MRI); 585 const RegisterBank *Src0Bank = RBI.getRegBank(Src0Reg, *MRI, TRI); 586 const RegisterBank *Src1Bank = RBI.getRegBank(Src1Reg, *MRI, TRI); 588 TRI.getRegClassForSizeOnBank(DstSize, *Src0Bank, *MRI); 590 TRI.getRegClassForSizeOnBank(InsSize, *Src1Bank, *MRI); 598 if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) || 599 !RBI.constrainGenericRegister(Src0Reg, *Src0RC, *MRI) || 600 !RBI.constrainGenericRegister(Src1Reg, *Src1RC, *MRI)) 633 MRI->setRegClass(Reg, TRI.getWaveMaskRegClass()); 721 unsigned Size = RBI.getSizeInBits(SrcReg, *MRI, TRI); 726 if (isSCC(CCReg, *MRI)) { 737 RBI.constrainGenericRegister(CCReg, AMDGPU::SReg_32RegClass, *MRI); 751 *TRI.getBoolRC(), *MRI); 928 = getBaseWithConstantOffset(*MRI, OrigOffset); 954 BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); 959 Register OverflowVal = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); 964 Register NewBaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); 983 LLT Ty = MRI->getType(VData); 1004 const bool Offen = !isZero(VOffset, *MRI); 1058 Register Undef = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); 1079 if (!MRI->getRegClassOrNull(Reg)) 1080 MRI->setRegClass(Reg, TRI.getWaveMaskRegClass()); 1097 unsigned Size = RBI.getSizeInBits(DstReg, *MRI, TRI); 1101 if (isSCC(CCReg, *MRI)) { 1110 if (!MRI->getRegClassOrNull(CCReg)) 1111 MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI)); 1111 MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI)); 1168 const LLT DstTy = MRI->getType(DstReg); 1169 const LLT SrcTy = MRI->getType(SrcReg); 1173 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); 1174 const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, *MRI, TRI); 1182 = TRI.getRegClassForSizeOnBank(SrcSize, *SrcRB, *MRI); 1184 = TRI.getRegClassForSizeOnBank(DstSize, *DstRB, *MRI); 1200 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI) || 1201 !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) { 1224 const LLT DstTy = MRI->getType(DstReg); 1225 const LLT SrcTy = MRI->getType(SrcReg); 1232 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI); 1245 Register TmpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); 1256 return RBI.constrainGenericRegister(DstReg, *DstRC, *MRI); 1302 if (!RBI.constrainGenericRegister(SrcReg, AMDGPU::SReg_32RegClass, *MRI)) 1311 return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_32RegClass, *MRI); 1320 Register ExtReg = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass); 1321 Register UndefReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); 1334 return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_64RegClass, *MRI); 1349 return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_32RegClass, *MRI); 1413 const RegisterBank *RB = MRI->getRegBankOrNull(I.getOperand(0).getReg()); 1416 Size = MRI->getType(DstReg).getSizeInBits(); 1418 const TargetRegisterClass *RC = TRI.getRegClassForReg(*MRI, DstReg); 1444 Register LoReg = MRI->createVirtualRegister(RC); 1445 Register HiReg = MRI->createVirtualRegister(RC); 1464 TRI.getConstrainedRegClassForOperand(ResInst->getOperand(0), *MRI); 1467 return RBI.constrainGenericRegister(DstReg, *DstRC, *MRI); 1541 const LLT PtrTy = MRI->getType(I.getOperand(1).getReg()); 1571 if (isSCC(CondReg, *MRI)) { 1576 } else if (isVCC(CondReg, *MRI)) { 1588 if (!MRI->getRegClassOrNull(CondReg)) 1589 MRI->setRegClass(CondReg, ConstrainRC); 1602 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); 1609 DstReg, IsVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::SReg_32RegClass, *MRI); 1621 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); 1622 const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, *MRI, TRI); 1629 LLT Ty = MRI->getType(DstReg); 1632 *MRI); 1634 *MRI); 1635 if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) || 1636 !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI)) 1640 Register ImmReg = MRI->createVirtualRegister(&RegRC); 1652 Register HiReg = MRI->createVirtualRegister(&RegRC); 1653 Register LoReg = MRI->createVirtualRegister(&RegRC); 1654 Register MaskLo = MRI->createVirtualRegister(&RegRC); 1783 MachineInstr *MI = MRI->getVRegDef(Src); 1788 MI = MRI->getVRegDef(Src); 1880 getAddrModeInfo(*Root.getParent(), *MRI, AddrInfo); 1901 getAddrModeInfo(*Root.getParent(), *MRI, AddrInfo); 1924 getAddrModeInfo(*MI, *MRI, AddrInfo); 1940 Register OffsetReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); 1963 const MachineInstr *OpDef = MRI->getVRegDef(Root.getReg()); 1968 getConstantVRegVal(OpDef->getOperand(2).getReg(), *MRI); 2008 if (mi_match(Root.getReg(), *MRI, m_ICst(Offset))) { 2009 Register HighBits = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); 2043 if (const MachineInstr *RootDef = MRI->getVRegDef(Root.getReg())) { 2044 if (isBaseWithConstantOffset(Root, *MRI)) { 2047 const MachineInstr *LHSDef = MRI->getVRegDef(LHS.getReg()); 2048 const MachineInstr *RHSDef = MRI->getVRegDef(RHS.getReg()); 2114 if (!mi_match(Root.getReg(), *MRI, m_ICst(Offset)) || 2137 const MachineInstr *RootDef = MRI->getVRegDef(Root.getReg()); 2146 if (isBaseWithConstantOffset(Root, *MRI)) { 2149 const MachineInstr *LHSDef = MRI->getVRegDef(LHS.getReg()); 2150 const MachineInstr *RHSDef = MRI->getVRegDef(RHS.getReg()); 2154 if (isDSOffsetLegal(*MRI, LHS, PossibleOffset, 16)) { 2166 } else if (mi_match(Root.getReg(), *MRI, m_ICst(ConstAddr))) {