reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  300   MachineBasicBlock *BB = I.getParent();
  302   Register DstReg = I.getOperand(0).getReg();
  303   const DebugLoc &DL = I.getDebugLoc();
  307   const bool Sub = I.getOpcode() == TargetOpcode::G_SUB;
  313         BuildMI(*BB, &I, DL, TII.get(Opc), DstReg)
  314         .add(I.getOperand(1))
  315         .add(I.getOperand(2));
  316       I.eraseFromParent();
  322       I.setDesc(TII.get(Opc));
  323       I.addOperand(*MF, MachineOperand::CreateImm(0));
  324       I.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
  325       return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
  332       = BuildMI(*BB, &I, DL, TII.get(Opc), DstReg)
  334       .add(I.getOperand(1))
  335       .add(I.getOperand(2))
  337     I.eraseFromParent();
  348   MachineOperand Lo1(getSubOperand64(I.getOperand(1), HalfRC, AMDGPU::sub0));
  349   MachineOperand Lo2(getSubOperand64(I.getOperand(2), HalfRC, AMDGPU::sub0));
  350   MachineOperand Hi1(getSubOperand64(I.getOperand(1), HalfRC, AMDGPU::sub1));
  351   MachineOperand Hi2(getSubOperand64(I.getOperand(2), HalfRC, AMDGPU::sub1));
  357     BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADD_U32), DstLo)
  360     BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADDC_U32), DstHi)
  366     BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_ADD_I32_e64), DstLo)
  371     MachineInstr *Addc = BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_ADDC_U32_e64), DstHi)
  382   BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)
  392   I.eraseFromParent();