reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
1218 bool Signed = I.getOpcode() == AMDGPU::G_SEXT; 1219 const DebugLoc &DL = I.getDebugLoc(); 1220 MachineBasicBlock &MBB = *I.getParent(); 1221 const Register DstReg = I.getOperand(0).getReg(); 1222 const Register SrcReg = I.getOperand(1).getReg(); 1246 BuildMI(MBB, I, DL, TII.get(AMDGPU::COPY), TmpReg) 1248 BuildMI(MBB, I, DL, TII.get(AMDGPU::COPY), AMDGPU::SCC) 1252 BuildMI(MBB, I, DL, TII.get(Opcode), DstReg) 1255 I.eraseFromParent(); 1264 BuildMI(MBB, I, DL, TII.get(AMDGPU::V_CNDMASK_B32_e64), DstReg) 1270 I.eraseFromParent(); 1274 if (I.getOpcode() == AMDGPU::G_ANYEXT) 1275 return selectCOPY(I); 1284 BuildMI(MBB, I, DL, TII.get(AMDGPU::V_AND_B32_e32), DstReg) 1287 I.eraseFromParent(); 1293 BuildMI(MBB, I, DL, TII.get(BFE), DstReg) 1297 I.eraseFromParent(); 1308 BuildMI(MBB, I, DL, TII.get(SextOpc), DstReg) 1310 I.eraseFromParent(); 1322 BuildMI(MBB, I, DL, TII.get(AMDGPU::IMPLICIT_DEF), UndefReg); 1323 BuildMI(MBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), ExtReg) 1329 BuildMI(MBB, I, DL, TII.get(BFE64), DstReg) 1333 I.eraseFromParent(); 1339 BuildMI(MBB, I, DL, TII.get(AMDGPU::S_AND_B32), DstReg) 1343 BuildMI(MBB, I, DL, TII.get(BFE32), DstReg) 1348 I.eraseFromParent();