reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
1034 MachineBasicBlock *BB = I.getParent(); 1035 unsigned IntrinsicID = I.getIntrinsicID(); 1038 int64_t Tgt = I.getOperand(1).getImm(); 1039 int64_t Enabled = I.getOperand(2).getImm(); 1040 int64_t Done = I.getOperand(7).getImm(); 1041 int64_t VM = I.getOperand(8).getImm(); 1043 MachineInstr *Exp = buildEXP(TII, &I, Tgt, I.getOperand(3).getReg(), 1043 MachineInstr *Exp = buildEXP(TII, &I, Tgt, I.getOperand(3).getReg(), 1044 I.getOperand(4).getReg(), 1045 I.getOperand(5).getReg(), 1046 I.getOperand(6).getReg(), 1049 I.eraseFromParent(); 1053 const DebugLoc &DL = I.getDebugLoc(); 1054 int64_t Tgt = I.getOperand(1).getImm(); 1055 int64_t Enabled = I.getOperand(2).getImm(); 1056 Register Reg0 = I.getOperand(3).getReg(); 1057 Register Reg1 = I.getOperand(4).getReg(); 1059 int64_t Done = I.getOperand(5).getImm(); 1060 int64_t VM = I.getOperand(6).getImm(); 1062 BuildMI(*BB, &I, DL, TII.get(AMDGPU::IMPLICIT_DEF), Undef); 1063 MachineInstr *Exp = buildEXP(TII, &I, Tgt, Reg0, Reg1, Undef, Undef, VM, 1066 I.eraseFromParent(); 1072 BuildMI(*BB, &I, I.getDebugLoc(), 1072 BuildMI(*BB, &I, I.getDebugLoc(), 1074 .add(I.getOperand(1)); 1076 Register Reg = I.getOperand(1).getReg(); 1077 I.eraseFromParent(); 1084 return selectStoreIntrinsic(I, false); 1086 return selectStoreIntrinsic(I, true); 1088 return selectImpl(I, *CoverageInfo);