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References

lib/Target/AMDGPU/AMDGPUISelLowering.cpp
 3899             CastedElts.push_back(DAG.getNode(ISD::BITCAST, DL, DestEltVT, Elt));
 3902           return DAG.getBuildVector(DestVT, SL, CastedElts);
 3919         SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
 3920                                  DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
 3921                                  DAG.getConstant(Hi_32(CVal), SL, MVT::i32));
 3922         return DAG.getNode(ISD::BITCAST, SL, DestVT, BV);
 3930       SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
 3931                                 DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
 3932                                 DAG.getConstant(Hi_32(CVal), SL, MVT::i32));
 3934       return DAG.getNode(ISD::BITCAST, SL, DestVT, Vec);
 3992       return DAG.getConstant(0, DL, MVT::i32);
 4007       unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
 4011       EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
 4019         return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
 4020                            DAG.getValueType(SmallVT));
 4023       return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
 4028         return constantFoldBFE<int32_t>(DAG,
 4035       return constantFoldBFE<uint32_t>(DAG,
 4044       SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32);
 4045       return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
 4055       TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
 4057       const TargetLowering &TLI = DAG.getTargetLoweringInfo();