reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
30 OS << "Reg " << printReg(getRegister(), TRI);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 4159 CreateLiveInRegister(DAG, RC, Arg.getRegister(), VT, SL) :
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp1789 if (!Arg->isRegister() || !Arg->getRegister().isValid()) 1792 assert(Arg->getRegister().isPhysical()); 1797 Register LiveIn = getLiveInRegister(MRI, Arg->getRegister(), Ty); 1824 EntryMBB.addLiveIn(Arg->getRegister()); 1826 B.buildCopy(LiveIn, Arg->getRegister());lib/Target/AMDGPU/SIISelLowering.cpp
1414 MRI.getLiveInVirtReg(InputPtrReg->getRegister()), PtrVT); 1560 return CreateLiveInRegister(DAG, RC, Reg->getRegister(), VT); 2495 RegsToPass.emplace_back(OutgoingArg->getRegister(), InputReg); 2561 RegsToPass.emplace_back(OutgoingArg->getRegister(), InputReg);lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
194 return ArgInfo.PrivateSegmentBuffer.getRegister(); 201 return ArgInfo.DispatchPtr.getRegister(); 208 return ArgInfo.QueuePtr.getRegister(); 216 return ArgInfo.KernargSegmentPtr.getRegister(); 223 return ArgInfo.DispatchID.getRegister(); 230 return ArgInfo.FlatScratchInit.getRegister(); 237 return ArgInfo.ImplicitBufferPtr.getRegister(); 442 OS << printReg(Arg.getRegister(), &TRI);lib/Target/AMDGPU/SIMachineFunctionInfo.h
545 return ArgInfo.WorkGroupIDX.getRegister(); 551 return ArgInfo.WorkGroupIDY.getRegister(); 557 return ArgInfo.WorkGroupIDZ.getRegister(); 563 return ArgInfo.WorkGroupInfo.getRegister(); 583 return ArgInfo.PrivateSegmentWaveByteOffset.getRegister(); 669 return Arg ? Arg->getRegister() : Register(); 693 return ArgInfo.PrivateSegmentWaveByteOffset.getRegister(); 739 return ArgInfo.QueuePtr.getRegister(); 743 return ArgInfo.ImplicitBufferPtr.getRegister(); 859 return ArgInfo.WorkGroupIDX.getRegister(); 862 return ArgInfo.WorkGroupIDY.getRegister(); 865 return ArgInfo.WorkGroupIDZ.getRegister();