reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

lib/Target/AMDGPU/AMDGPUISelLowering.h

   26 struct ArgDescriptor;

References

lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp

   80 std::pair<const ArgDescriptor *, const TargetRegisterClass *>

lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h

   47   static ArgDescriptor createRegister(Register Reg, unsigned Mask = ~0u) {
   51   static ArgDescriptor createStack(unsigned Offset, unsigned Mask = ~0u) {
   55   static ArgDescriptor createArg(const ArgDescriptor &Arg, unsigned Mask) {
   55   static ArgDescriptor createArg(const ArgDescriptor &Arg, unsigned Mask) {
   92 inline raw_ostream &operator<<(raw_ostream &OS, const ArgDescriptor &Arg) {
  124   ArgDescriptor PrivateSegmentBuffer;
  125   ArgDescriptor DispatchPtr;
  126   ArgDescriptor QueuePtr;
  127   ArgDescriptor KernargSegmentPtr;
  128   ArgDescriptor DispatchID;
  129   ArgDescriptor FlatScratchInit;
  130   ArgDescriptor PrivateSegmentSize;
  133   ArgDescriptor WorkGroupIDX;
  134   ArgDescriptor WorkGroupIDY;
  135   ArgDescriptor WorkGroupIDZ;
  136   ArgDescriptor WorkGroupInfo;
  137   ArgDescriptor PrivateSegmentWaveByteOffset;
  141   ArgDescriptor ImplicitArgPtr;
  144   ArgDescriptor ImplicitBufferPtr = 0;
  147   ArgDescriptor WorkItemIDX;
  148   ArgDescriptor WorkItemIDY;
  149   ArgDescriptor WorkItemIDZ;
  151   std::pair<const ArgDescriptor *, const TargetRegisterClass *>

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

 4155                                              const ArgDescriptor &Arg) const {

lib/Target/AMDGPU/AMDGPUISelLowering.h

  311                          const ArgDescriptor &Arg) const;

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

 1788                                          const ArgDescriptor *Arg) const {
 1843   const ArgDescriptor *Arg;
 2023   const ArgDescriptor *Arg;

lib/Target/AMDGPU/AMDGPULegalizerInfo.h

   82                       const ArgDescriptor *Arg) const;

lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

 1087       Arg = ArgDescriptor::createRegister(Reg);
 1089       Arg = ArgDescriptor::createStack(A->StackOffset);
 1092       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());

lib/Target/AMDGPU/SIISelLowering.cpp

 1405   const ArgDescriptor *InputPtrReg;
 1556   const ArgDescriptor *Reg;
 1625     Info.setWorkItemIDX(ArgDescriptor::createRegister(Reg));
 1633     Info.setWorkItemIDY(ArgDescriptor::createRegister(Reg));
 1641     Info.setWorkItemIDZ(ArgDescriptor::createRegister(Reg));
 1649 static ArgDescriptor allocateVGPR32Input(CCState &CCInfo, unsigned Mask = ~0u,
 1650                                          ArgDescriptor Arg = ArgDescriptor()) {
 1652     return ArgDescriptor::createArg(Arg, Mask);
 1661     return ArgDescriptor::createStack(Offset, Mask);
 1671   return ArgDescriptor::createRegister(Reg, Mask);
 1674 static ArgDescriptor allocateSGPR32InputImpl(CCState &CCInfo,
 1688   return ArgDescriptor::createRegister(Reg);
 1691 static ArgDescriptor allocateSGPR32Input(CCState &CCInfo) {
 1695 static ArgDescriptor allocateSGPR64Input(CCState &CCInfo) {
 1704   ArgDescriptor Arg;
 2468     const ArgDescriptor *OutgoingArg;
 2475     const ArgDescriptor *IncomingArg;
 2506   const ArgDescriptor *OutgoingArg;
 2520   const ArgDescriptor *IncomingArgX
 2522   const ArgDescriptor *IncomingArgY
 2524   const ArgDescriptor *IncomingArgZ
 2553     ArgDescriptor IncomingArg = ArgDescriptor::createArg(
 2553     ArgDescriptor IncomingArg = ArgDescriptor::createArg(

lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

   79       ArgDescriptor::createRegister(ScratchRSrcReg);
   81       ArgDescriptor::createRegister(ScratchWaveOffsetReg);
  126           ArgDescriptor::createRegister(AMDGPU::SGPR5);
  191     ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
  198   ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
  205   ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
  213     = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
  220   ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
  227   ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
  234   ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(

lib/Target/AMDGPU/SIMachineFunctionInfo.h

  543     ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
  549     ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
  555     ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
  561     ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
  567   void setWorkItemIDX(ArgDescriptor Arg) {
  571   void setWorkItemIDY(ArgDescriptor Arg) {
  575   void setWorkItemIDZ(ArgDescriptor Arg) {
  581       = ArgDescriptor::createRegister(getNextSystemSGPR());
  587     ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
  662   std::pair<const ArgDescriptor *, const TargetRegisterClass *>