reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc
10853     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::SVEDataVector, 1, 0, 8>());
10860     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::SVEDataVector, 1, 0, 16>());
10867     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::SVEDataVector, 1, 0, 32>());
10874     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::SVEDataVector, 1, 0, 64>());
10881     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::SVEDataVector, 2, 0, 8>());
10888     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::SVEDataVector, 2, 0, 16>());
10895     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::SVEDataVector, 2, 0, 32>());
10902     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::SVEDataVector, 2, 0, 64>());
10909     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::SVEDataVector, 3, 0, 8>());
10916     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::SVEDataVector, 3, 0, 16>());
10923     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::SVEDataVector, 3, 0, 32>());
10930     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::SVEDataVector, 3, 0, 64>());
10937     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::SVEDataVector, 4, 0, 8>());
10944     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::SVEDataVector, 4, 0, 16>());
10951     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::SVEDataVector, 4, 0, 32>());
10958     DiagnosticPredicate DP(Operand.isTypedVectorList<RegKind::SVEDataVector, 4, 0, 64>());
40810     return tryParseVectorList<RegKind::SVEDataVector>(Operands);
40812     return tryParseVectorList<RegKind::SVEDataVector>(Operands);
40814     return tryParseVectorList<RegKind::SVEDataVector>(Operands);
40816     return tryParseVectorList<RegKind::SVEDataVector>(Operands);
40818     return tryParseVectorList<RegKind::SVEDataVector>(Operands);
40820     return tryParseVectorList<RegKind::SVEDataVector>(Operands);
40822     return tryParseVectorList<RegKind::SVEDataVector>(Operands);
40824     return tryParseVectorList<RegKind::SVEDataVector>(Operands);
40826     return tryParseVectorList<RegKind::SVEDataVector>(Operands);
40828     return tryParseVectorList<RegKind::SVEDataVector>(Operands);
40830     return tryParseVectorList<RegKind::SVEDataVector>(Operands);
40832     return tryParseVectorList<RegKind::SVEDataVector>(Operands);
40834     return tryParseVectorList<RegKind::SVEDataVector>(Operands);
40836     return tryParseVectorList<RegKind::SVEDataVector>(Operands);
40838     return tryParseVectorList<RegKind::SVEDataVector>(Operands);
40840     return tryParseVectorList<RegKind::SVEDataVector>(Operands);
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
 1046       RK = RegKind::SVEDataVector;
 1078     if (Kind != k_Register || Reg.Kind != RegKind::SVEDataVector)
 1837     assert((Kind == RegKind::NeonVector || Kind == RegKind::SVEDataVector ||
 2161   case RegKind::SVEDataVector:
 2256     return Kind == RegKind::SVEDataVector ? RegNum : 0;
 5399     RegisterKind = RegKind::SVEDataVector;
 5401         tryParseVectorRegister(RegNum, Kind, RegKind::SVEDataVector);
 5670       tryParseVectorRegister(RegNum, Kind, RegKind::SVEDataVector);
 5678   const auto &KindRes = parseVectorKind(Kind, RegKind::SVEDataVector);
 5687         RegNum, RegKind::SVEDataVector, ElementWidth, S, S, getContext()));
 5706       RegNum, RegKind::SVEDataVector, ElementWidth, S, Ext->getEndLoc(),