reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
639 getLdStRegOp(MI).getReg() == AArch64::WZR; 859 MachineOperand RegOp0 = getLdStRegOp(*RtMI); 860 MachineOperand RegOp1 = getLdStRegOp(*Rt2MI); 875 Register Reg = getLdStRegOp(*I).getReg(); 949 Register LdRt = getLdStRegOp(*LoadI).getReg(); 950 const MachineOperand &StMO = getLdStRegOp(*StoreI); 951 Register StRt = getLdStRegOp(*StoreI).getReg(); 1138 ModifiedRegUnits.available(getLdStRegOp(MI).getReg())) { 1223 Register Reg = getLdStRegOp(FirstMI).getReg(); 1287 (IsPromotableZeroStore && Reg != getLdStRegOp(MI).getReg())) { 1317 if (MayLoad && Reg == getLdStRegOp(MI).getReg()) { 1328 if (ModifiedRegUnits.available(getLdStRegOp(MI).getReg()) && 1330 !UsedRegUnits.available(getLdStRegOp(MI).getReg())) && 1340 if (ModifiedRegUnits.available(getLdStRegOp(FirstMI).getReg()) && 1342 !UsedRegUnits.available(getLdStRegOp(FirstMI).getReg())) && 1400 .add(getLdStRegOp(*Update)) 1401 .add(getLdStRegOp(*I)) 1409 .add(getLdStRegOp(*Update)) 1410 .add(getLdStRegOp(*I, 0)) 1411 .add(getLdStRegOp(*I, 1)) 1512 Register DestReg = getLdStRegOp(MemMI, i).getReg(); 1566 Register DestReg = getLdStRegOp(MemMI, i).getReg();