reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
2467 (AArch64::GPR32spRegClass.contains(SrcReg) || SrcReg == AArch64::WZR)) { 2467 (AArch64::GPR32spRegClass.contains(SrcReg) || SrcReg == AArch64::WZR)) { 2470 if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) { 2476 unsigned SrcRegX = TRI->getMatchingSuperReg(SrcReg, AArch64::sub_32, 2486 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); 2489 .addReg(SrcReg, getKillRegState(KillSrc)) 2493 } else if (SrcReg == AArch64::WZR && Subtarget.hasZeroCycleZeroingGP()) { 2502 unsigned SrcRegX = TRI->getMatchingSuperReg(SrcReg, AArch64::sub_32, 2511 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); 2516 .addReg(SrcReg, getKillRegState(KillSrc)); 2524 AArch64::PPRRegClass.contains(SrcReg)) { 2527 .addReg(SrcReg) // Pg 2528 .addReg(SrcReg) 2529 .addReg(SrcReg, getKillRegState(KillSrc)); 2535 AArch64::ZPRRegClass.contains(SrcReg)) { 2538 .addReg(SrcReg) 2539 .addReg(SrcReg, getKillRegState(KillSrc)); 2544 (AArch64::GPR64spRegClass.contains(SrcReg) || SrcReg == AArch64::XZR)) { 2544 (AArch64::GPR64spRegClass.contains(SrcReg) || SrcReg == AArch64::XZR)) { 2545 if (DestReg == AArch64::SP || SrcReg == AArch64::SP) { 2548 .addReg(SrcReg, getKillRegState(KillSrc)) 2551 } else if (SrcReg == AArch64::XZR && Subtarget.hasZeroCycleZeroingGP()) { 2559 .addReg(SrcReg, getKillRegState(KillSrc)); 2566 AArch64::DDDDRegClass.contains(SrcReg)) { 2569 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8, 2576 AArch64::DDDRegClass.contains(SrcReg)) { 2579 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8, 2586 AArch64::DDRegClass.contains(SrcReg)) { 2588 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8, 2595 AArch64::QQQQRegClass.contains(SrcReg)) { 2598 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8, 2605 AArch64::QQQRegClass.contains(SrcReg)) { 2608 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8, 2615 AArch64::QQRegClass.contains(SrcReg)) { 2617 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8, 2623 AArch64::XSeqPairsClassRegClass.contains(SrcReg)) { 2625 copyGPRRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRXrs, 2631 AArch64::WSeqPairsClassRegClass.contains(SrcReg)) { 2633 copyGPRRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRWrs, 2639 AArch64::FPR128RegClass.contains(SrcReg)) { 2642 .addReg(SrcReg) 2643 .addReg(SrcReg, getKillRegState(KillSrc)); 2647 .addReg(SrcReg, getKillRegState(KillSrc)) 2660 AArch64::FPR64RegClass.contains(SrcReg)) { 2664 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::dsub, 2664 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::dsub, 2667 .addReg(SrcReg) 2668 .addReg(SrcReg, getKillRegState(KillSrc)); 2671 .addReg(SrcReg, getKillRegState(KillSrc)); 2677 AArch64::FPR32RegClass.contains(SrcReg)) { 2681 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::ssub, 2681 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::ssub, 2684 .addReg(SrcReg) 2685 .addReg(SrcReg, getKillRegState(KillSrc)); 2688 .addReg(SrcReg, getKillRegState(KillSrc)); 2694 AArch64::FPR16RegClass.contains(SrcReg)) { 2698 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub, 2698 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub, 2701 .addReg(SrcReg) 2702 .addReg(SrcReg, getKillRegState(KillSrc)); 2706 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub, 2706 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub, 2709 .addReg(SrcReg, getKillRegState(KillSrc)); 2715 AArch64::FPR8RegClass.contains(SrcReg)) { 2719 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::bsub, 2719 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::bsub, 2722 .addReg(SrcReg) 2723 .addReg(SrcReg, getKillRegState(KillSrc)); 2727 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::bsub, 2727 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::bsub, 2730 .addReg(SrcReg, getKillRegState(KillSrc)); 2737 AArch64::GPR64RegClass.contains(SrcReg)) { 2739 .addReg(SrcReg, getKillRegState(KillSrc)); 2743 AArch64::FPR64RegClass.contains(SrcReg)) { 2745 .addReg(SrcReg, getKillRegState(KillSrc)); 2750 AArch64::GPR32RegClass.contains(SrcReg)) { 2752 .addReg(SrcReg, getKillRegState(KillSrc)); 2756 AArch64::FPR32RegClass.contains(SrcReg)) { 2758 .addReg(SrcReg, getKillRegState(KillSrc)); 2763 assert(AArch64::GPR64RegClass.contains(SrcReg) && "Invalid NZCV copy"); 2766 .addReg(SrcReg, getKillRegState(KillSrc)) 2771 if (SrcReg == AArch64::NZCV) {