reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
65825 /*160295*/ /*SwitchOpcode*/ 27, TARGET_VAL(AArch64ISD::VASHR),// ->160325 65894 /*160421*/ /*SwitchOpcode*/ 28, TARGET_VAL(AArch64ISD::VASHR),// ->160452 68581 /*165249*/ /*SwitchOpcode*/ 33|128,1/*161*/, TARGET_VAL(AArch64ISD::VASHR),// ->165414 68929 /*165915*/ /*SwitchOpcode*/ 34|128,1/*162*/, TARGET_VAL(AArch64ISD::VASHR),// ->166081 88533 /*203776*/ OPC_SwitchOpcode /*2 cases */, 72|128,1/*200*/, TARGET_VAL(AArch64ISD::VASHR),// ->203981 88565 /*203834*/ OPC_CheckOpcode, TARGET_VAL(AArch64ISD::VASHR), 88587 /*203870*/ OPC_CheckOpcode, TARGET_VAL(AArch64ISD::VASHR), 88599 /*203892*/ /*SwitchOpcode*/ 85, TARGET_VAL(AArch64ISD::VASHR),// ->203980 88678 /*204028*/ OPC_CheckOpcode, TARGET_VAL(AArch64ISD::VASHR), 88685 /*204039*/ OPC_CheckOpcode, TARGET_VAL(AArch64ISD::VASHR), 88706 /*204074*/ OPC_CheckOpcode, TARGET_VAL(AArch64ISD::VASHR), 88713 /*204085*/ OPC_CheckOpcode, TARGET_VAL(AArch64ISD::VASHR), 88724 /*204106*/ /*SwitchOpcode*/ 106, TARGET_VAL(AArch64ISD::VASHR),// ->204215 88755 /*204158*/ OPC_CheckOpcode, TARGET_VAL(AArch64ISD::VASHR), 88777 /*204194*/ OPC_CheckOpcode, TARGET_VAL(AArch64ISD::VASHR), 95729 /*216949*/ /*SwitchOpcode*/ 36|128,1/*164*/, TARGET_VAL(AArch64ISD::VASHR),// ->217117 99818 /*224680*/ /*SwitchOpcode*/ 73, TARGET_VAL(AArch64ISD::VASHR),// ->224756 108369 /*241957*/ /*SwitchOpcode*/ 5|128,1/*133*/, TARGET_VAL(AArch64ISD::VASHR),// ->242094gen/lib/Target/AArch64/AArch64GenFastISel.inc
8502 case AArch64ISD::VASHR: return fastEmit_AArch64ISD_VASHR_ri_Predicate_vecshiftR64(VT, RetVT, Op0, Op0IsKill, imm1); 8874 case AArch64ISD::VASHR: return fastEmit_AArch64ISD_VASHR_ri_Predicate_vecshiftR8(VT, RetVT, Op0, Op0IsKill, imm1); 8998 case AArch64ISD::VASHR: return fastEmit_AArch64ISD_VASHR_ri_Predicate_vecshiftR16(VT, RetVT, Op0, Op0IsKill, imm1); 9122 case AArch64ISD::VASHR: return fastEmit_AArch64ISD_VASHR_ri_Predicate_vecshiftR32(VT, RetVT, Op0, Op0IsKill, imm1);lib/Target/AArch64/AArch64ISelLowering.cpp
1238 case AArch64ISD::VASHR: return "AArch64ISD::VASHR"; 8028 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR; 9279 if (Shift.getOpcode() != AArch64ISD::VASHR || !Shift.hasOneUse() ||