reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/Target/AArch64/AArch64ISelLowering.cpp
 6953       return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
 6965       unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
 6966       Lane -= Idx * VT.getVectorNumElements() / 2;
 6968     } else if (VT.getSizeInBits() == 64)
 6971     return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, dl, MVT::i64));
 6974   if (isREVMask(ShuffleMask, VT, 64))
 6976   if (isREVMask(ShuffleMask, VT, 32))
 6978   if (isREVMask(ShuffleMask, VT, 16))
 6983   if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
 6989   } else if (V2->isUndef() && isSingletonEXTMask(ShuffleMask, VT, Imm)) {
 6996   if (isZIPMask(ShuffleMask, VT, WhichResult)) {
 7000   if (isUZPMask(ShuffleMask, VT, WhichResult)) {
 7004   if (isTRNMask(ShuffleMask, VT, WhichResult)) {
 7009   if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
 7013   if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
 7017   if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
 7036       SrcLane -= VT.getVectorNumElements();
 7040     EVT ScalarVT = VT.getVectorElementType();
 7046         ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
 7053   unsigned NumElts = VT.getVectorNumElements();