reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
3867 switch (VA.getLocInfo()) { 3873 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); 3876 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); 3884 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); 3887 assert(VA.getValVT() == MVT::i32 && "only expect 32 -> 64 upper bits"); 3888 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); 3889 Arg = DAG.getNode(ISD::SHL, DL, VA.getLocVT(), Arg, 3890 DAG.getConstant(32, DL, VA.getLocVT())); 3893 Arg = DAG.getBitcast(VA.getLocVT(), Arg); 3896 Arg = DAG.getZExtOrTrunc(Arg, DL, VA.getLocVT()); 3899 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg); 3902 assert(VA.getValVT().isScalableVector() && 3907 if (VA.isRegLoc()) { 3910 assert(VA.getLocVT() == MVT::i64 && 3916 if (RegsUsed.count(VA.getLocReg())) { 3924 return Elt.first == VA.getLocReg(); 3932 [&VA](MachineFunction::ArgRegPair ArgReg) { 3933 return ArgReg.Reg == VA.getLocReg(); 3937 RegsToPass.emplace_back(VA.getLocReg(), Arg); 3938 RegsUsed.insert(VA.getLocReg()); 3941 CSInfo.emplace_back(VA.getLocReg(), i); 3944 assert(VA.isMemLoc()); 3953 : VA.getValVT().getSizeInBits(); 3960 unsigned LocMemOffset = VA.getLocMemOffset(); 3999 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 || 3999 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 || 4000 VA.getValVT() == MVT::i16) 4001 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);