|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
lib/Target/AArch64/AArch64ISelLowering.cpp 6947 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
6953 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
6967 V1 = WidenVector(V1.getOperand(Idx), DAG);
6969 V1 = WidenVector(V1, DAG);
6971 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, dl, MVT::i64));
6971 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, dl, MVT::i64));
6975 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
6977 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
6979 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
6987 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
6988 DAG.getConstant(Imm, dl, MVT::i32));
6991 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
6992 DAG.getConstant(Imm, dl, MVT::i32));
6998 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
7002 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
7006 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
7011 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
7015 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
7019 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
7022 if (SDValue Concat = tryFormConcatFromShuffle(Op, DAG))
7030 SDValue DstLaneV = DAG.getConstant(Anomaly, dl, MVT::i64);
7038 SDValue SrcLaneV = DAG.getConstant(SrcLane, dl, MVT::i64);
7045 return DAG.getNode(
7047 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
7070 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
7073 return GenerateTBL(Op, ShuffleMask, DAG);