|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
Declarations
include/llvm/MC/MCParser/MCTargetAsmParser.h 361 const MCSubtargetInfo &getSTI() const;
References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc15303 MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, getSTI(), Info)) {
gen/lib/Target/PowerPC/PPCGenAsmMatcher.inc 7185 MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, getSTI(), Info)) {
lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp 165 emitInlineAsmEnd(STI, &TAP->getSTI());
lib/MC/MCParser/AsmParser.cpp 3039 const MCSubtargetInfo &STI = MCT.getSTI();
lib/MC/MCParser/MCTargetAsmParser.cpp 22 MCSubtargetInfo &STICopy = getContext().getSubtargetCopy(getSTI());
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp 255 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
2688 getSTI().getFeatureBits()[AArch64::FeatureSVE])
2900 else if (!IC->haveFeatures(getSTI().getFeatureBits())) {
2910 else if (!DC->haveFeatures(getSTI().getFeatureBits())) {
2920 else if (!AT->haveFeatures(getSTI().getFeatureBits())) {
2930 else if (!TLBI->haveFeatures(getSTI().getFeatureBits())) {
2940 else if (!PRCTX->haveFeatures(getSTI().getFeatureBits())) {
3045 if (SysReg && SysReg->haveFeatures(getSTI().getFeatureBits())) {
3053 if (PState && PState->haveFeatures(getSTI().getFeatureBits()))
4708 if (getSTI().getFeatureBits()[AArch64::FeatureZCZeroingFPWorkaround] &&
4821 Out.EmitInstruction(Inst, getSTI());
5221 if (!getSTI().isCPUStringValid(CPU)) {
5311 getParser().getStreamer().EmitInstruction(Inst, getSTI());
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp 1121 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());
1123 if (ISA.Major >= 6 && AMDGPU::IsaInfo::hasCodeObjectV3(&getSTI())) {
1140 if (ISA.Major >= 6 && AMDGPU::IsaInfo::hasCodeObjectV3(&getSTI())) {
1149 return AMDGPU::hasXNACK(getSTI());
1153 return AMDGPU::hasMIMG_R128(getSTI());
1157 return AMDGPU::hasPackedD16(getSTI());
1161 return AMDGPU::isSI(getSTI());
1165 return AMDGPU::isCI(getSTI());
1169 return AMDGPU::isVI(getSTI());
1173 return AMDGPU::isGFX9(getSTI());
1177 return AMDGPU::isGFX10(getSTI());
1216 return getSTI().getFeatureBits();
1864 Inst.addOperand(MCOperand::createReg(AMDGPU::getMCReg(getReg(), AsmParser->getSTI())));
2291 if (AMDGPU::getIsaVersion(getSTI().getCPU()).Major < 6)
2328 if (AMDGPU::IsaInfo::hasCodeObjectV3(&getSTI())) {
3519 Out.EmitInstruction(Inst, getSTI());
3526 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
3581 if (getSTI().getTargetTriple().getArch() != Triple::amdgcn)
3593 IsaInfo::streamIsaVersion(&getSTI(), ExpectedTargetOS);
3614 IsaVersion Version = getIsaVersion(getSTI().getCPU());
3623 IsaInfo::getAddressableNumSGPRs(&getSTI());
3630 IsaInfo::getNumExtraSGPRs(&getSTI(), VCCUsed, FlatScrUsed, XNACKUsed);
3641 IsaInfo::getNumVGPRBlocks(&getSTI(), NumVGPRs, EnableWavefrontSize32);
3642 SGPRBlocks = IsaInfo::getNumSGPRBlocks(&getSTI(), NumSGPRs);
3648 if (getSTI().getTargetTriple().getArch() != Triple::amdgcn)
3651 if (getSTI().getTargetTriple().getOS() != Triple::AMDHSA)
3658 kernel_descriptor_t KD = getDefaultAmdhsaKernelDescriptor(&getSTI());
3662 IsaVersion IVersion = getIsaVersion(getSTI().getCPU());
3930 getSTI(), KernelName, KD, NextFreeVGPR, NextFreeSGPR, ReserveVCC,
3956 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());
4058 AMDGPU::initDefaultAMDKernelCodeT(Header, &getSTI());
4093 if (!AMDGPU::IsaInfo::hasCodeObjectV3(&getSTI()))
4099 if (getSTI().getTargetTriple().getArch() != Triple::amdgcn) {
4109 IsaInfo::streamIsaVersion(&getSTI(), ISAVersionStreamFromSTI);
4127 AMDGPU::IsaInfo::hasCodeObjectV3(&getSTI())
4133 if (getSTI().getTargetTriple().getOS() != Triple::AMDHSA) {
4144 if (IsaInfo::hasCodeObjectV3(&getSTI())) {
4213 if (getSTI().getTargetTriple().getOS() != Triple::AMDPAL) {
4259 unsigned LocalMemorySize = AMDGPU::IsaInfo::getLocalMemorySize(&getSTI());
4301 if (AMDGPU::IsaInfo::hasCodeObjectV3(&getSTI())) {
4889 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());
4925 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());
4985 if (HwReg.IsSymbolic && !isValidHwreg(HwReg.Id, getSTI())) {
5079 if (!isValidMsgId(Msg.Id, getSTI(), Strict)) {
lib/Target/ARM/AsmParser/ARMAsmParser.cpp 248 Out.EmitInstruction(ITInst, getSTI());
253 Out.EmitInstruction(Inst, getSTI());
449 return getSTI().getFeatureBits()[ARM::ModeThumb];
453 return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2];
457 return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2];
461 return getSTI().getFeatureBits()[ARM::HasV4TOps];
465 return getSTI().getFeatureBits()[ARM::FeatureThumb2];
469 return getSTI().getFeatureBits()[ARM::HasV6Ops];
473 return getSTI().getFeatureBits()[ARM::HasV6T2Ops];
477 return getSTI().getFeatureBits()[ARM::HasV6MOps];
481 return getSTI().getFeatureBits()[ARM::HasV7Ops];
485 return getSTI().getFeatureBits()[ARM::HasV8Ops];
489 return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps];
493 return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps];
496 return getSTI().getFeatureBits()[ARM::HasV8_1MMainlineOps];
499 return getSTI().getFeatureBits()[ARM::HasMVEIntegerOps];
502 return getSTI().getFeatureBits()[ARM::HasMVEFloatOps];
505 return getSTI().getFeatureBits()[ARM::Feature8MSecExt];
509 return !getSTI().getFeatureBits()[ARM::FeatureNoARM];
513 return getSTI().getFeatureBits()[ARM::FeatureDSP];
517 return getSTI().getFeatureBits()[ARM::FeatureD32];
521 return getSTI().getFeatureBits()[ARM::HasV8_1aOps];
525 return getSTI().getFeatureBits()[ARM::FeatureRAS];
537 return getSTI().getFeatureBits()[ARM::FeatureMClass];
4177 if (!isValidCoprocessorNumber(Num, getSTI().getFeatureBits()))
4950 if (!TheReg || !TheReg->hasRequiredFeatures(getSTI().getFeatureBits()))
10473 Out.EmitInstruction(Inst, getSTI());
10480 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
10899 if (!getSTI().isCPUStringValid(CPU))
lib/Target/BPF/AsmParser/BPFAsmParser.cpp 298 Out.EmitInstruction(Inst, getSTI());
lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp 164 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
472 HexagonMCChecker Check(getContext(), MII, getSTI(), MCB, *RI);
474 bool CheckOk = HexagonMCInstrInfo::canonicalizePacket(MII, getSTI(),
485 Out.EmitInstruction(MCB, getSTI());
517 if (getSTI().getFeatureBits()[Hexagon::FeatureMemNoShuf])
811 if (!getSTI().getFeatureBits()[Hexagon::ArchV62])
1303 if (!getSTI().getFeatureBits()[Hexagon::ArchV65]) {
lib/Target/Mips/AsmParser/MipsAsmParser.cpp 460 if (!(getSTI().getFeatureBits()[Feature])) {
469 if (getSTI().getFeatureBits()[Feature]) {
479 AssemblerOptions.front()->setFeatures(getSTI().getFeatureBits());
484 AssemblerOptions.front()->setFeatures(getSTI().getFeatureBits());
517 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
521 std::make_unique<MipsAssemblerOptions>(getSTI().getFeatureBits()));
525 std::make_unique<MipsAssemblerOptions>(getSTI().getFeatureBits()));
543 if (getSTI().getCPU() == "mips64r6" && inMicroMipsMode())
554 return getSTI().getFeatureBits()[Mips::FeatureGP64Bit];
558 return getSTI().getFeatureBits()[Mips::FeatureFP64Bit];
566 return getSTI().getFeatureBits()[Mips::FeatureFPXX];
570 return !(getSTI().getFeatureBits()[Mips::FeatureNoOddSPReg]);
574 return getSTI().getFeatureBits()[Mips::FeatureMicroMips];
578 return getSTI().getFeatureBits()[Mips::FeatureMips1];
582 return getSTI().getFeatureBits()[Mips::FeatureMips2];
586 return getSTI().getFeatureBits()[Mips::FeatureMips3];
590 return getSTI().getFeatureBits()[Mips::FeatureMips4];
594 return getSTI().getFeatureBits()[Mips::FeatureMips5];
598 return getSTI().getFeatureBits()[Mips::FeatureMips32];
602 return getSTI().getFeatureBits()[Mips::FeatureMips64];
606 return getSTI().getFeatureBits()[Mips::FeatureMips32r2];
610 return getSTI().getFeatureBits()[Mips::FeatureMips64r2];
614 return (getSTI().getFeatureBits()[Mips::FeatureMips32r3]);
618 return (getSTI().getFeatureBits()[Mips::FeatureMips64r3]);
622 return (getSTI().getFeatureBits()[Mips::FeatureMips32r5]);
626 return (getSTI().getFeatureBits()[Mips::FeatureMips64r5]);
630 return getSTI().getFeatureBits()[Mips::FeatureMips32r6];
634 return getSTI().getFeatureBits()[Mips::FeatureMips64r6];
638 return getSTI().getFeatureBits()[Mips::FeatureDSP];
642 return getSTI().getFeatureBits()[Mips::FeatureDSPR2];
646 return getSTI().getFeatureBits()[Mips::FeatureDSPR3];
650 return getSTI().getFeatureBits()[Mips::FeatureMSA];
654 return (getSTI().getFeatureBits()[Mips::FeatureCnMips]);
662 return getSTI().getFeatureBits()[Mips::FeatureMips16];
666 return getSTI().getFeatureBits()[Mips::FeatureUseTCCInDIV];
670 return getSTI().getFeatureBits()[Mips::FeatureSoftFloat];
673 return getSTI().getFeatureBits()[Mips::FeatureMT];
677 return getSTI().getFeatureBits()[Mips::FeatureCRC];
681 return getSTI().getFeatureBits()[Mips::FeatureVirt];
685 return getSTI().getFeatureBits()[Mips::FeatureGINV];
6610 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp 1099 if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) {
1145 Out.EmitInstruction(Inst, getSTI());
1150 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1612 if (getSTI().getFeatureBits()[PPC::FeatureBookE] &&
lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 51 bool isRV64() const { return getSTI().hasFeature(RISCV::Feature64Bit); }
52 bool isRV32E() const { return getSTI().hasFeature(RISCV::FeatureRV32E); }
142 if (!(getSTI().getFeatureBits()[Feature])) {
150 if (getSTI().getFeatureBits()[Feature]) {
158 FeatureBitStack.push_back(getSTI().getFeatureBits());
1071 if (!SysReg->haveRequiredFeatures(getSTI().getFeatureBits())) {
1392 if (getSTI().getFeatureBits()[RISCV::FeatureRelax]) {
1589 bool Res = compressInst(CInst, Inst, getSTI(), S.getContext());
1591 S.EmitInstruction((Res ? CInst : Inst), getSTI());
lib/Target/Sparc/AsmParser/SparcAsmParser.cpp 102 return getSTI().getTargetTriple().getArch() == Triple::sparcv9;
122 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
603 Out.EmitInstruction(I, getSTI());
lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp 446 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
1121 Parser.getStreamer().EmitInstruction(Inst, getSTI());
1255 Out.EmitInstruction(Inst, getSTI());
1286 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp 801 Out.EmitInstruction(Inst, getSTI());
lib/Target/X86/AsmParser/X86AsmParser.cpp 923 return getSTI().getFeatureBits()[X86::Mode64Bit];
927 return getSTI().getFeatureBits()[X86::Mode32Bit];
931 return getSTI().getFeatureBits()[X86::Mode16Bit];
978 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
3042 Out.EmitInstruction(Inst, getSTI());