reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
758 assert(Op.getScalarValueSizeInBits() == BitWidth && 762 assert((!Op.getValueType().isVector() || 763 NumElts == Op.getValueType().getVectorNumElements()) && 768 SDLoc dl(Op); 775 if (Op.isUndef()) 778 if (Op.getOpcode() == ISD::Constant) { 780 Known.One = cast<ConstantSDNode>(Op)->getAPIntValue(); 786 EVT VT = Op.getValueType(); 787 if (!Op.getNode()->hasOneUse() && !AssumeSingleUse) { 791 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth); 800 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT)); 807 switch (Op.getOpcode()) { 812 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT)); 815 SDValue Src = Op.getOperand(0); 826 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth); 829 LoadSDNode *LD = cast<LoadSDNode>(Op); 831 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth); 837 SDValue Vec = Op.getOperand(0); 838 SDValue Scl = Op.getOperand(1); 839 auto *CIdx = dyn_cast<ConstantSDNode>(Op.getOperand(2)); 851 return TLO.CombineTo(Op, Vec); 875 SDValue Base = Op.getOperand(0); 876 SDValue Sub = Op.getOperand(1); 884 if (isa<ConstantSDNode>(Op.getOperand(2))) { 885 const APInt &Idx = Op.getConstantOperandAPInt(2); 915 SDValue Src = Op.getOperand(0); 916 ConstantSDNode *SubIdx = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 931 EVT SubVT = Op.getOperand(0).getValueType(); 932 unsigned NumSubVecs = Op.getNumOperands(); 937 if (SimplifyDemandedBits(Op.getOperand(i), DemandedBits, DemandedSubElts, 949 ArrayRef<int> ShuffleMask = cast<ShuffleVectorSDNode>(Op)->getMask(); 973 SDValue Op0 = Op.getOperand(0); 974 SDValue Op1 = Op.getOperand(1); 1002 return TLO.CombineTo(Op, NewOp); 1008 SDValue Op0 = Op.getOperand(0); 1009 SDValue Op1 = Op.getOperand(1); 1021 return TLO.CombineTo(Op, Op0); 1025 if (ShrinkDemandedConstant(Op, ~LHSKnown.Zero & DemandedBits, TLO)) 1036 return TLO.CombineTo(Op, Xor); 1058 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1); 1059 return TLO.CombineTo(Op, NewOp); 1066 return TLO.CombineTo(Op, Op0); 1068 return TLO.CombineTo(Op, Op1); 1071 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, dl, VT)); 1073 if (ShrinkDemandedConstant(Op, ~Known2.Zero & DemandedBits, TLO)) 1076 if (ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO)) 1086 SDValue Op0 = Op.getOperand(0); 1087 SDValue Op1 = Op.getOperand(1); 1107 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1); 1108 return TLO.CombineTo(Op, NewOp); 1115 return TLO.CombineTo(Op, Op0); 1117 return TLO.CombineTo(Op, Op1); 1119 if (ShrinkDemandedConstant(Op, DemandedBits, TLO)) 1122 if (ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO)) 1132 SDValue Op0 = Op.getOperand(0); 1133 SDValue Op1 = Op.getOperand(1); 1153 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1); 1154 return TLO.CombineTo(Op, NewOp); 1161 return TLO.CombineTo(Op, Op0); 1163 return TLO.CombineTo(Op, Op1); 1165 if (ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO)) 1172 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, VT, Op0, Op1)); 1188 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, Op0, ANDC)); 1198 return TLO.CombineTo(Op, New); 1201 if (ShrinkDemandedConstant(Op, DemandedBits, TLO)) 1210 if (SimplifyDemandedBits(Op.getOperand(2), DemandedBits, Known, TLO, 1213 if (SimplifyDemandedBits(Op.getOperand(1), DemandedBits, Known2, TLO, 1220 if (ShrinkDemandedConstant(Op, DemandedBits, TLO)) 1228 if (SimplifyDemandedBits(Op.getOperand(3), DemandedBits, Known, TLO, 1231 if (SimplifyDemandedBits(Op.getOperand(2), DemandedBits, Known2, TLO, 1238 if (ShrinkDemandedConstant(Op, DemandedBits, TLO)) 1246 SDValue Op0 = Op.getOperand(0); 1247 SDValue Op1 = Op.getOperand(1); 1248 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1262 return TLO.CombineTo(Op, Op0); 1274 SDValue Op0 = Op.getOperand(0); 1275 SDValue Op1 = Op.getOperand(1); 1284 return TLO.CombineTo(Op, Op0); 1305 Op, TLO.DAG.getNode(Opc, dl, VT, Op0.getOperand(0), NewSA)); 1318 ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO)) 1336 Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, NarrowShl)); 1357 Op, TLO.DAG.getNode(ISD::SHL, dl, VT, NewExt, NewSA)); 1371 SDValue Op0 = Op.getOperand(0); 1372 SDValue Op1 = Op.getOperand(1); 1381 return TLO.CombineTo(Op, Op0); 1388 if (Op->getFlags().hasExact()) 1411 Op, TLO.DAG.getNode(Opc, dl, VT, Op0.getOperand(0), NewSA)); 1430 SDValue Op0 = Op.getOperand(0); 1431 SDValue Op1 = Op.getOperand(1); 1438 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1)); 1447 return TLO.CombineTo(Op, Op0); 1453 if (Op->getFlags().hasExact()) 1473 Flags.setExact(Op->getFlags().hasExact()); 1475 Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1, Flags)); 1483 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, NewSA)); 1494 SDValue Op0 = Op.getOperand(0); 1495 SDValue Op1 = Op.getOperand(1); 1496 SDValue Op2 = Op.getOperand(2); 1497 bool IsFSHL = (Op.getOpcode() == ISD::FSHL); 1532 SDValue Src = Op.getOperand(0); 1542 SDValue Op0 = Op.getOperand(0); 1543 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1561 return TLO.CombineTo(Op, 1568 return TLO.CombineTo(Op, Op0); 1586 Op, TLO.DAG.getZeroExtendInReg(Op0, dl, ExVT.getScalarType())); 1599 EVT HalfVT = Op.getOperand(0).getValueType(); 1607 if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownLo, TLO, Depth + 1)) 1610 if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownHi, TLO, Depth + 1)) 1622 SDValue Src = Op.getOperand(0); 1626 bool IsVecInReg = Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG; 1635 return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src)); 1640 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src)); 1655 SDValue Src = Op.getOperand(0); 1659 bool IsVecInReg = Op.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG; 1668 return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src)); 1673 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src)); 1697 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src)); 1703 SDValue Src = Op.getOperand(0); 1707 bool IsVecInReg = Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG; 1714 return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src)); 1727 SDValue Src = Op.getOperand(0); 1740 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::TRUNCATE, dl, VT, NewSrc)); 1777 Op, TLO.DAG.getNode(ISD::SRL, dl, VT, NewTrunc, Shift)); 1789 EVT ZVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1791 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | DemandedBits, Known, 1800 SDValue Src = Op.getOperand(0); 1801 SDValue Idx = Op.getOperand(1); 1827 SDValue Src = Op.getOperand(0); 1834 DemandedBits == APInt::getSignMask(Op.getValueSizeInBits()) && 1845 unsigned OpVTSizeInBits = Op.getValueSizeInBits(); 1848 unsigned ShVal = Op.getValueSizeInBits() - 1; 1850 return TLO.CombineTo(Op, 1913 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth); 1923 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1); 1923 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1); 1924 SDNodeFlags Flags = Op.getNode()->getFlags(); 1932 ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO)) { 1939 TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1, Flags); 1940 return TLO.CombineTo(Op, NewOp); 1957 TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1, Flags); 1958 return TLO.CombineTo(Op, NewOp); 1976 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Neg1, Flags); 1977 return TLO.CombineTo(Op, NewOp); 1983 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { 1984 if (SimplifyDemandedBitsForTargetNode(Op, DemandedBits, DemandedElts, 1991 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth); 1999 const SDNode *N = Op.getNode(); 2010 return TLO.CombineTo(Op, TLO.DAG.getConstant(Known.One, dl, VT));