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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
lib/CodeGen/SelectionDAG/TargetLowering.cpp 3055 EVT OpVT = N0.getValueType();
3058 if (SDValue Fold = DAG.FoldSetCC(VT, N0, N1, Cond, dl))
3064 if (isConstOrConstSplat(N0) &&
3066 isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
3067 return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
3073 if (!isConstOrConstSplat(N0) && !isConstOrConstSplat(N1) &&
3075 isCondCodeLegal(SwappedCC, N0.getSimpleValueType())) &&
3076 DAG.getNodeIfExists(ISD::SUB, DAG.getVTList(OpVT), { N1, N0 } ) &&
3077 !DAG.getNodeIfExists(ISD::SUB, DAG.getVTList(OpVT), { N0, N1 } ))
3078 return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
3086 if (N0.getOpcode() == ISD::SRL && (C1.isNullValue() || C1.isOneValue()) &&
3087 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
3088 N0.getOperand(1).getOpcode() == ISD::Constant) {
3089 const APInt &ShAmt = N0.getConstantOperandAPInt(1);
3091 ShAmt == Log2_32(N0.getValueSizeInBits())) {
3101 SDValue Zero = DAG.getConstant(0, dl, N0.getValueType());
3102 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
3107 SDValue CTPOP = N0;
3109 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
3109 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
3110 CTPOP = N0.getOperand(0);
3113 (N0 == CTPOP ||
3114 N0.getValueSizeInBits() > Log2_32_Ceil(CTPOP.getValueSizeInBits()))) {
3148 DCI.isBeforeLegalize() && N0->hasOneUse()) {
3149 unsigned MinBits = N0.getValueSizeInBits();
3152 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
3154 MinBits = N0->getOperand(0).getValueSizeInBits();
3155 PreExt = N0->getOperand(0);
3156 } else if (N0->getOpcode() == ISD::AND) {
3158 if (auto *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
3161 PreExt = N0->getOperand(0);
3163 } else if (N0->getOpcode() == ISD::SIGN_EXTEND) {
3165 MinBits = N0->getOperand(0).getValueSizeInBits();
3166 PreExt = N0->getOperand(0);
3168 } else if (auto *LN0 = dyn_cast<LoadSDNode>(N0)) {
3172 PreExt = N0;
3176 PreExt = N0;
3209 SDValue TopSetCC = N0->getOperand(0);
3210 unsigned N0Opc = N0->getOpcode();
3216 isExtendedTrueVal(N1C, N0->getValueType(0), SExt))) {
3239 N0.getOpcode() == ISD::AND && C1 == 0 &&
3240 N0.getNode()->hasOneUse() &&
3241 isa<LoadSDNode>(N0.getOperand(0)) &&
3242 N0.getOperand(0).getNode()->hasOneUse() &&
3243 isa<ConstantSDNode>(N0.getOperand(1))) {
3244 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
3248 unsigned origWidth = N0.getValueSizeInBits();
3254 const APInt &Mask = N0.getConstantOperandAPInt(1);
3294 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
3295 unsigned InSize = N0.getOperand(0).getValueSizeInBits();
3331 EVT newVT = N0.getOperand(0).getValueType();
3339 SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0),
3341 return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType());
3348 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3350 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
3352 EVT ExtDstTy = N0.getValueType();
3361 EVT Op0Ty = N0.getOperand(0).getValueType();
3363 ZextOp = N0.getOperand(0);
3366 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
3381 if (N0.getOpcode() == ISD::SETCC &&
3382 isTypeLegal(VT) && VT.bitsLE(N0.getValueType()) &&
3383 (N0.getValueType() == MVT::i1 ||
3384 getBooleanContents(N0.getOperand(0).getValueType()) ==
3388 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
3390 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
3392 N0.getOperand(0).getValueType().isInteger());
3394 isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType()))
3395 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
3395 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
3398 if ((N0.getOpcode() == ISD::XOR ||
3399 (N0.getOpcode() == ISD::AND &&
3400 N0.getOperand(0).getOpcode() == ISD::XOR &&
3401 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
3401 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
3402 isa<ConstantSDNode>(N0.getOperand(1)) &&
3403 cast<ConstantSDNode>(N0.getOperand(1))->isOne()) {
3406 unsigned BitWidth = N0.getValueSizeInBits();
3407 if (DAG.MaskedValueIsZero(N0,
3412 if (N0.getOpcode() == ISD::XOR) {
3413 Val = N0.getOperand(0);
3415 assert(N0.getOpcode() == ISD::AND &&
3416 N0.getOperand(0).getOpcode() == ISD::XOR);
3418 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
3419 N0.getOperand(0).getOperand(0),
3420 N0.getOperand(1));
3428 getBooleanContents(N0.getValueType()) ==
3430 SDValue Op0 = N0;
3471 if (N0.getOpcode() == ISD::UREM && N1C->isNullValue() &&
3473 KnownBits XKnown = DAG.computeKnownBits(N0.getOperand(0));
3474 KnownBits YKnown = DAG.computeKnownBits(N0.getOperand(1));
3476 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1, Cond);
3480 optimizeSetCCOfSignedTruncationCheck(VT, N0, N1, Cond, DCI, dl))
3513 return DAG.getSetCC(dl, VT, N0,
3533 return DAG.getSetCC(dl, VT, N0,
3548 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
3552 return DAG.getSetCC(dl, VT, N0,
3553 DAG.getConstant(MinVal, dl, N0.getValueType()),
3566 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
3570 return DAG.getSetCC(dl, VT, N0,
3571 DAG.getConstant(MaxVal, dl, N0.getValueType()),
3580 VT, N0, N1, Cond, DCI, dl))
3591 return DAG.getSetCC(dl, VT, N0,
3601 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
3611 EVT ShValTy = N0.getValueType();
3616 N0.getOpcode() == ISD::AND) {
3618 if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3626 DAG.getNode(ISD::SRL, dl, ShValTy, N0,
3636 DAG.getNode(ISD::SRL, dl, ShValTy, N0,
3647 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
3647 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
3648 if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3653 EVT ShiftTy = getShiftAmountTy(N0.getValueType(), DL,
3655 EVT CmpTy = N0.getValueType();
3656 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
3684 EVT ShiftTy = getShiftAmountTy(N0.getValueType(), DL,
3686 EVT CmpTy = N0.getValueType();
3687 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
3696 if (!isa<ConstantFPSDNode>(N0) && isa<ConstantFPSDNode>(N1)) {
3705 return DAG.getSetCC(dl, VT, N0, N0, Cond);
3705 return DAG.getSetCC(dl, VT, N0, N0, Cond);
3708 if (N0.getOpcode() == ISD::FNEG) {
3711 isCondCodeLegal(SwapCond, N0.getSimpleValueType())) {
3712 SDValue NegN1 = DAG.getNode(ISD::FNEG, dl, N0.getValueType(), N1);
3713 return DAG.getSetCC(dl, VT, N0.getOperand(0), NegN1, SwapCond);
3719 if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
3726 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
3727 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
3729 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
3730 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
3732 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
3733 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
3735 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
3736 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
3739 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
3740 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
3742 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
3743 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
3745 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
3746 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
3748 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
3749 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
3755 if (N0 == N1) {
3758 assert(!N0.getValueType().isInteger() &&
3772 isCondCodeLegal(NewCond, N0.getSimpleValueType())))
3773 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
3777 N0.getValueType().isInteger()) {
3778 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
3778 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
3779 N0.getOpcode() == ISD::XOR) {
3781 if (N0.getOpcode() == N1.getOpcode()) {
3782 if (N0.getOperand(0) == N1.getOperand(0))
3783 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
3784 if (N0.getOperand(1) == N1.getOperand(1))
3785 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
3786 if (isCommutativeBinOp(N0.getOpcode())) {
3788 if (N0.getOperand(0) == N1.getOperand(1))
3789 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
3791 if (N0.getOperand(1) == N1.getOperand(0))
3792 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
3802 if (auto *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3804 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
3804 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
3805 return DAG.getSetCC(dl, VT, N0.getOperand(0),
3808 dl, N0.getValueType()), Cond);
3812 if (N0.getOpcode() == ISD::XOR)
3815 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
3817 DAG.getSetCC(dl, VT, N0.getOperand(0),
3820 dl, N0.getValueType()),
3825 if (auto *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
3826 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
3826 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
3828 DAG.getSetCC(dl, VT, N0.getOperand(1),
3831 dl, N0.getValueType()),
3845 if (!LegalRHSImm || N0.hasOneUse())
3846 if (SDValue V = foldSetCCWithBinOp(VT, N0, N1, Cond, dl, DCI))
3852 if (SDValue V = foldSetCCWithBinOp(VT, N1, N0, Cond, dl, DCI))
3855 if (SDValue V = foldSetCCWithAnd(VT, N0, N1, Cond, dl, DCI))
3860 if ((N0.getOpcode() == ISD::UREM || N0.getOpcode() == ISD::SREM) &&
3860 if ((N0.getOpcode() == ISD::UREM || N0.getOpcode() == ISD::SREM) &&
3861 N0.hasOneUse() && (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3867 if (N0.getOpcode() == ISD::UREM) {
3868 if (SDValue Folded = buildUREMEqFold(VT, N0, N1, Cond, DCI, dl))
3870 } else if (N0.getOpcode() == ISD::SREM) {
3871 if (SDValue Folded = buildSREMEqFold(VT, N0, N1, Cond, DCI, dl))
3878 if (N0.getValueType().getScalarType() == MVT::i1 && foldBooleans) {
3883 Temp = DAG.getNode(ISD::XOR, dl, OpVT, N0, N1);
3884 N0 = DAG.getNOT(dl, Temp, OpVT);
3889 N0 = DAG.getNode(ISD::XOR, dl, OpVT, N0, N1);
3889 N0 = DAG.getNode(ISD::XOR, dl, OpVT, N0, N1);
3893 Temp = DAG.getNOT(dl, N0, OpVT);
3894 N0 = DAG.getNode(ISD::AND, dl, OpVT, N1, Temp);
3901 N0 = DAG.getNode(ISD::AND, dl, OpVT, N0, Temp);
3901 N0 = DAG.getNode(ISD::AND, dl, OpVT, N0, Temp);
3907 Temp = DAG.getNOT(dl, N0, OpVT);
3908 N0 = DAG.getNode(ISD::OR, dl, OpVT, N1, Temp);
3915 N0 = DAG.getNode(ISD::OR, dl, OpVT, N0, Temp);
3915 N0 = DAG.getNode(ISD::OR, dl, OpVT, N0, Temp);
3920 DCI.AddToWorklist(N0.getNode());
3923 N0 = DAG.getNode(ExtendCode, dl, VT, N0);
3923 N0 = DAG.getNode(ExtendCode, dl, VT, N0);
3925 return N0;