reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

include/llvm/CodeGen/RegisterScavenging.h

  163   Register scavengeRegister(const TargetRegisterClass *RC,

References

include/llvm/CodeGen/RegisterScavenging.h

  168     return scavengeRegister(RegClass, MBBI, SPAdj, AllowSpill);

lib/Target/AMDGPU/SIInstrInfo.cpp

 6212   Register UnusedCarry = RS.scavengeRegister(RI.getBoolRC(), I, 0, false);

lib/Target/AMDGPU/SIRegisterInfo.cpp

  663       SOffset = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0, false);
  821         TmpVGPR = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);
  917         TmpVGPR = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);
 1100           RS->scavengeRegister(&AMDGPU::SReg_32_XM0RegClass, MI, 0, false);
 1108           RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);
 1123               RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MIB, 0);
 1141                 RS->scavengeRegister(&AMDGPU::SReg_32_XM0RegClass, MIB, 0, false);
 1161                 RS->scavengeRegister(&AMDGPU::SReg_32_XM0RegClass, MI, 0, false);
 1229         Register TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);

lib/Target/ARC/ARCRegisterInfo.cpp

   66       BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj);

lib/Target/Lanai/LanaiRegisterInfo.cpp

  175       Reg = RS->scavengeRegister(&Lanai::GPRRegClass, II, SPAdj);

lib/Target/XCore/XCoreRegisterInfo.cpp

  100   unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
  172     ScratchBase = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
  177   unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);