reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

include/llvm/CodeGen/MachineRegisterInfo.h
  670   void setRegClass(unsigned Reg, const TargetRegisterClass *RC);

References

lib/CodeGen/GlobalISel/IRTranslator.cpp
 1168   MRI->setRegClass(DstReg, TRI->getPointerRegClass(*MF));
lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
  140   MRI.setRegClass(Reg, &RC);
lib/CodeGen/MIRParser/MIRParser.cpp
  589       MRI.setRegClass(Reg, Info.D.RC);
lib/CodeGen/MachineLICM.cpp
 1399           MRI->setRegClass(Dup->getOperand(Defs[j]).getReg(), OrigRCs[j]);
lib/CodeGen/MachineRegisterInfo.cpp
   80   MRI.setRegClass(Reg, NewRC);
  142   setRegClass(Reg, NewRC);
lib/CodeGen/ModuloSchedule.cpp
 1728     MRI.setRegClass(R, MRI.getRegClass(PhiR));
lib/CodeGen/RegisterCoalescer.cpp
 1359     MRI->setRegClass(DstReg, NewRC);
 1913     MRI->setRegClass(CP.getDstReg(), CP.getNewRC());
lib/CodeGen/SelectionDAG/InstrEmitter.cpp
  658           MRI->setRegClass(NewVReg, SRC);
lib/CodeGen/TailDuplicator.cpp
  413               MRI->setRegClass(VI->second.Reg, ConstrRC);
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  141         MRI->setRegClass(SrcReg, TRI.getConstrainedRegClassForOperand(Src, *MRI));
  281       MRI->setRegClass(Src0.getReg(), RC);
  283       MRI->setRegClass(Src1.getReg(), RC);
  426     MRI.setRegClass(Dst1Reg, &AMDGPU::SReg_32RegClass);
  633       MRI->setRegClass(Reg, TRI.getWaveMaskRegClass());
 1080       MRI->setRegClass(Reg, TRI.getWaveMaskRegClass());
 1111         MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI));
 1589     MRI->setRegClass(CondReg, ConstrainRC);
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
 1627   B.getMRI()->setRegClass(PCReg, &AMDGPU::SReg_64RegClass);
 2125       MRI.setRegClass(Def, TRI->getWaveMaskRegClass());
 2126       MRI.setRegClass(Use, TRI->getWaveMaskRegClass());
 2146       MRI.setRegClass(Reg, TRI->getWaveMaskRegClass());
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  839               MRI.setRegClass(UnmergePiece, &AMDGPU::VReg_64RegClass);
  840               MRI.setRegClass(CurrentLaneOpRegLo, &AMDGPU::SReg_32_XM0RegClass);
  841               MRI.setRegClass(CurrentLaneOpRegHi, &AMDGPU::SReg_32_XM0RegClass);
  858               MRI.setRegClass(CurrentLaneOpReg, &AMDGPU::SReg_64_XEXECRegClass);
  871               MRI.setRegClass(UnmergePiece, &AMDGPU::VGPR_32RegClass);
  872               MRI.setRegClass(CurrentLaneOpReg, &AMDGPU::SReg_32_XM0RegClass);
lib/Target/AMDGPU/SIFixSGPRCopies.cpp
  222   MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg)));
  274   MRI.setRegClass(DstReg, DstRC);
  806     MRI->setRegClass(PHIRes, TRI->getEquivalentAGPRClass(RC0));
lib/Target/AMDGPU/SIISelLowering.cpp
10421         MRI.setRegClass(Op.getReg(), NewRC);
lib/Target/AMDGPU/SILowerI1Copies.cpp
  570     MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass
  691       MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass
lib/Target/Mips/MipsInstructionSelector.cpp
  461     MRI.setRegClass(MI->getOperand(0).getReg(),
lib/Target/PowerPC/PPCFastISel.cpp
  416     MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass);
 1315           MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
 1319           MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
 1332             MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
 1341             MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
 2420     MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass);
 2422     MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass);
lib/Target/PowerPC/PPCInstrInfo.cpp
 3841         MRI.setRegClass(RegToModify, NewRC);
lib/Target/PowerPC/PPCMIPeephole.cpp
  764         MRI->setRegClass(DominatorReg, TRC);
lib/Target/X86/X86DomainReassignment.cpp
  511     MRI->setRegClass(Reg, getDstRC(MRI->getRegClass(Reg), Domain));