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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
include/llvm/CodeGen/MachineRegisterInfo.h 691 const TargetRegisterClass *constrainRegClass(unsigned Reg,
References
lib/CodeGen/GlobalISel/RegisterBankInfo.cpp 132 return MRI.constrainRegClass(Reg, &RC);
lib/CodeGen/MachineBasicBlock.cpp 510 if (!MRI.constrainRegClass(VirtReg, RC))
lib/CodeGen/MachineLICM.cpp 1396 if (!MRI->constrainRegClass(DupReg, MRI->getRegClass(Reg))) {
lib/CodeGen/MachineLoopUtils.cpp 67 MRI.constrainRegClass(R, MRI.getRegClass(Use->getReg()));
lib/CodeGen/ModuloSchedule.cpp 1183 MRI.constrainRegClass(ReplaceReg, MRI.getRegClass(OldReg));
1230 MRI.constrainRegClass(MI.getOperand(1).getReg(),
1475 MRI.constrainRegClass(R, MRI.getRegClass(InitReg.getValue()));
1485 MRI.constrainRegClass(R, MRI.getRegClass(*InitReg));
lib/CodeGen/OptimizePHIs.cpp 180 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg)))
lib/CodeGen/PeepholeOptimizer.cpp 581 MRI->constrainRegClass(DstReg, DstRC);
lib/CodeGen/RegisterCoalescer.cpp 840 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
lib/CodeGen/SelectionDAG/FastISel.cpp 2025 if (!MRI.constrainRegClass(Op, RegClass)) {
2233 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 318 = MRI->constrainRegClass(VReg, OpRC, MinRCSize);
457 RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 529 MRI.constrainRegClass(To, MRI.getRegClass(From));
675 MRI.constrainRegClass(To, MRI.getRegClass(From));
lib/CodeGen/TailDuplicator.cpp 241 MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) {
418 ConstrRC = MRI->constrainRegClass(VI->second.Reg, OrigRC);
lib/CodeGen/TargetInstrInfo.cpp 815 MRI.constrainRegClass(RegA, RC);
817 MRI.constrainRegClass(RegB, RC);
819 MRI.constrainRegClass(RegX, RC);
821 MRI.constrainRegClass(RegY, RC);
823 MRI.constrainRegClass(RegC, RC);
lib/CodeGen/TwoAddressInstructionPass.cpp 1488 MRI->constrainRegClass(DstReg, RC);
1601 MRI->constrainRegClass(RegA, RC);
lib/CodeGen/UnreachableBlockElim.cpp 186 MRI.constrainRegClass(InputReg, MRI.getRegClass(OutputReg)) &&
lib/Target/AArch64/AArch64ConditionalCompares.cpp 643 MRI->constrainRegClass(HeadCond[2].getReg(),
690 MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(),
693 MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg(),
lib/Target/AArch64/AArch64InstrInfo.cpp 579 MRI.constrainRegClass(SrcReg, &AArch64::GPR64spRegClass);
585 MRI.constrainRegClass(SrcReg, &AArch64::GPR32spRegClass);
625 if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) {
629 } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) {
633 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR64RegClass)) {
636 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR32RegClass)) {
664 MRI.constrainRegClass(TrueReg, RC);
665 MRI.constrainRegClass(FalseReg, RC);
1078 !MRI->constrainRegClass(Reg, OpRegCstraints))
2831 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR32RegClass);
2841 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass);
2962 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR32RegClass);
2972 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR64RegClass);
3198 MF.getRegInfo().constrainRegClass(DstReg, &AArch64::GPR64RegClass);
3202 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass);
4011 MRI.constrainRegClass(ResultReg, RC);
4013 MRI.constrainRegClass(SrcReg0, RC);
4015 MRI.constrainRegClass(SrcReg1, RC);
4017 MRI.constrainRegClass(SrcReg2, RC);
4077 MRI.constrainRegClass(ResultReg, RC);
4079 MRI.constrainRegClass(SrcReg0, RC);
4081 MRI.constrainRegClass(SrcReg1, RC);
4083 MRI.constrainRegClass(VR, RC);
lib/Target/AArch64/AArch64RegisterInfo.cpp 418 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
lib/Target/AMDGPU/R600MachineScheduler.cpp 373 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_XRegClass);
376 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_YRegClass);
379 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_ZRegClass);
382 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_WRegClass);
lib/Target/AMDGPU/SIInstrInfo.cpp 1074 MRI.constrainRegClass(SrcReg, &AMDGPU::SReg_32_XM0RegClass);
1199 MRI.constrainRegClass(DestReg, &AMDGPU::SReg_32_XM0RegClass);
lib/Target/AMDGPU/SILowerI1Copies.cpp 486 MRI->constrainRegClass(Reg, &AMDGPU::SReg_1_XEXECRegClass);
lib/Target/ARM/A15SDOptimizer.cpp 642 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
lib/Target/ARM/ARMBaseInstrInfo.cpp 2251 if (!MRI.constrainRegClass(DestReg, PreviousClass))
lib/Target/ARM/ARMBaseRegisterInfo.cpp 646 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 2324 MRI->constrainRegClass(FirstReg, TRC);
2325 MRI->constrainRegClass(SecondReg, TRC);
lib/Target/ARM/Thumb2InstrInfo.cpp 164 MRI->constrainRegClass(SrcReg, &ARM::GPRPairnospRegClass);
205 MRI->constrainRegClass(DestReg, &ARM::GPRPairnospRegClass);
657 if (!MRI->constrainRegClass(FrameReg, RegClass))
lib/Target/Lanai/LanaiInstrInfo.cpp 509 if (!MRI.constrainRegClass(DestReg, PreviousClass))
lib/Target/PowerPC/PPCRegisterInfo.cpp 1235 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
1261 MRI.constrainRegClass(BaseReg,
lib/Target/PowerPC/PPCVSXFMAMutate.cpp 236 if (!MRI.constrainRegClass(KilledProdReg,
lib/Target/SystemZ/SystemZInstrInfo.cpp 587 MRI.constrainRegClass(DstReg, &SystemZ::GR32BitRegClass);
lib/Target/X86/X86FlagsCopyLowering.cpp 953 MRI->constrainRegClass(Reg, &X86::GR32_ABCDRegClass);
lib/Target/X86/X86InstrInfo.cpp 725 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
929 !MF.getRegInfo().constrainRegClass(Src.getReg(),
4647 auto *NewRC = MRI.constrainRegClass(