reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
600 MIRBuilder.setInstr(MI); 602 uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 605 switch (MI.getOpcode()) { 620 Register DstReg = MI.getOperand(0).getReg(); 625 MI.eraseFromParent(); 629 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 630 const APInt &Val = MI.getOperand(1).getCImm()->getValue(); 654 insertParts(MI.getOperand(0).getReg(), 657 MI.eraseFromParent(); 664 Register SrcReg = MI.getOperand(1).getReg(); 679 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {SrcReg, Shift.getReg(0)}); 680 MI.eraseFromParent(); 687 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); 696 SmallVector<Register, 4> Srcs = {MI.getOperand(1).getReg()}; 699 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), Srcs); 700 MI.eraseFromParent(); 707 uint64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 713 auto Unmerge = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1).getReg()); 714 MIRBuilder.buildCopy(MI.getOperand(0).getReg(), Unmerge.getReg(0)); 715 MI.eraseFromParent(); 728 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs); 729 extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs); 746 Register DstReg = MI.getOperand(0).getReg(); 751 MI.eraseFromParent(); 763 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs); 764 extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs); 782 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs); 783 MI.eraseFromParent(); 788 return narrowScalarMul(MI, NarrowTy); 790 return narrowScalarExtract(MI, TypeIdx, NarrowTy); 792 return narrowScalarInsert(MI, TypeIdx, NarrowTy); 794 const auto &MMO = **MI.memoperands_begin(); 795 Register DstReg = MI.getOperand(0).getReg(); 802 auto &MMO = **MI.memoperands_begin(); 803 MIRBuilder.buildLoad(TmpReg, MI.getOperand(1).getReg(), MMO); 805 MI.eraseFromParent(); 809 return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy); 813 bool ZExt = MI.getOpcode() == TargetOpcode::G_ZEXTLOAD; 814 Register DstReg = MI.getOperand(0).getReg(); 815 Register PtrReg = MI.getOperand(1).getReg(); 818 auto &MMO = **MI.memoperands_begin(); 835 MI.eraseFromParent(); 839 const auto &MMO = **MI.memoperands_begin(); 841 Register SrcReg = MI.getOperand(0).getReg(); 854 auto &MMO = **MI.memoperands_begin(); 856 MIRBuilder.buildStore(TmpReg, MI.getOperand(1).getReg(), MMO); 857 MI.eraseFromParent(); 861 return reduceLoadStoreWidth(MI, 0, NarrowTy); 864 return narrowScalarSelect(MI, TypeIdx, NarrowTy); 877 return narrowScalarBasic(MI, TypeIdx, NarrowTy); 882 return narrowScalarShift(MI, TypeIdx, NarrowTy); 891 Observer.changingInstr(MI); 892 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT); 893 Observer.changedInstr(MI); 899 Observer.changingInstr(MI); 900 narrowScalarSrc(MI, NarrowTy, 1); 901 Observer.changedInstr(MI); 907 Observer.changingInstr(MI); 908 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT); 909 Observer.changedInstr(MI); 916 SrcRegs.resize(MI.getNumOperands() / 2); 917 Observer.changingInstr(MI); 918 for (unsigned i = 1; i < MI.getNumOperands(); i += 2) { 919 MachineBasicBlock &OpMBB = *MI.getOperand(i + 1).getMBB(); 921 extractParts(MI.getOperand(i).getReg(), NarrowTy, NumParts, 924 MachineBasicBlock &MBB = *MI.getParent(); 925 MIRBuilder.setInsertPt(MBB, MI); 930 for (unsigned j = 1; j < MI.getNumOperands(); j += 2) 931 MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1)); 934 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs); 935 Observer.changedInstr(MI); 936 MI.eraseFromParent(); 944 int OpIdx = MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT ? 2 : 3; 945 Observer.changingInstr(MI); 946 narrowScalarSrc(MI, NarrowTy, OpIdx); 947 Observer.changedInstr(MI); 951 uint64_t SrcSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); 955 Observer.changingInstr(MI); 958 MIRBuilder.buildUnmerge({LHSL, LHSH}, MI.getOperand(2).getReg()); 962 MIRBuilder.buildUnmerge({RHSL, RHSH}, MI.getOperand(3).getReg()); 965 static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); 966 LLT ResTy = MRI.getType(MI.getOperand(0).getReg()); 973 MIRBuilder.buildICmp(Pred, MI.getOperand(0).getReg(), Or, Zero); 980 MIRBuilder.buildSelect(MI.getOperand(0).getReg(), CmpHEQ, CmpLU, CmpH); 982 Observer.changedInstr(MI); 983 MI.eraseFromParent(); 990 if (!MI.getOperand(2).isImm()) 992 int64_t SizeInBits = MI.getOperand(2).getImm(); 997 Observer.changingInstr(MI); 1000 MachineOperand &MO1 = MI.getOperand(1); 1004 MachineOperand &MO2 = MI.getOperand(0); 1009 Observer.changedInstr(MI); 1034 MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1).getReg()); 1073 Register DstReg = MI.getOperand(0).getReg(); 1075 MI.eraseFromParent();