|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc72469 return isShiftedInt<30,2>(v) && !isShiftedInt<29,3>(v);
72469 return isShiftedInt<30,2>(v) && !isShiftedInt<29,3>(v);
72497 return isShiftedInt<4, 3>(N->getSExtValue());
72534 return isShiftedInt<4, 0>(N->getSExtValue());
72541 return isShiftedInt<4, 1>(N->getSExtValue());
72548 return isShiftedInt<4, 2>(N->getSExtValue());
72640 return isShiftedInt<32, 0>(N->getSExtValue());
72738 return isShiftedInt<8, 0>(N->getSExtValue());
72758 return isShiftedInt<6, 0>(N->getSExtValue());
72882 return isShiftedInt<32, 2>(N->getSExtValue());
gen/lib/Target/RISCV/RISCVGenAsmWriter.inc 2819 return isShiftedInt<12, 1>(Imm);
2827 return isShiftedInt<20, 1>(Imm);
gen/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc 49 return isShiftedInt<6, 4>(Imm) && (Imm != 0);
56 return isShiftedInt<8, 1>(Imm);
97 return isShiftedInt<11, 1>(Imm);
923 return isShiftedInt<12, 1>(Imm);
931 return isShiftedInt<20, 1>(Imm);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc13986 return isShiftedInt<20, 12>(Imm);
gen/lib/Target/RISCV/RISCVGenGlobalISel.inc 157 return (Imm != 0) && isShiftedInt<6, 4>(Imm);
167 return isShiftedInt<11, 1>(Imm);
177 return isShiftedInt<20, 12>(Imm);
192 return isShiftedInt<8, 1>(Imm);
lib/Target/Hexagon/HexagonInstrInfo.cpp 3900 isShiftedInt<6,3>(MI.getOperand(1).getImm()))
lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp 552 if (!isShiftedInt<7, 0>(Value))
lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h 193 return isShiftedInt<N, S>(minConstant(MCI, Index));
lib/Target/Mips/AsmParser/MipsAsmParser.cpp 1308 isShiftedInt<Bits, ShiftAmount>(getConstantMemOff())))
1312 return IsReloc && isShiftedInt<Bits, ShiftAmount>(Res.getConstant());
1359 isShiftedInt<Bits, ShiftLeftAmount>(getConstantImm()))
1367 return Success && isShiftedInt<Bits, ShiftLeftAmount>(Res.getConstant());
lib/Target/PowerPC/PPCISelLowering.cpp14429 if (isShiftedInt<16, 16>(Value))
lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 289 IsValid = isShiftedInt<N - 1, 1>(Imm);
534 return IsConstantImm && (Imm != 0) && isShiftedInt<6, 4>(Imm) &&
lib/Target/RISCV/RISCVInstrInfo.cpp 520 Ok = isShiftedInt<12, 1>(Imm);
526 Ok = isShiftedInt<20, 1>(Imm);
unittests/Support/MathExtrasTest.cpp 469 EXPECT_TRUE((isShiftedInt<1, 0>(0)));
470 EXPECT_TRUE((isShiftedInt<1, 0>(-1)));
471 EXPECT_FALSE((isShiftedInt<1, 0>(2)));
472 EXPECT_FALSE((isShiftedInt<1, 0>(3)));
473 EXPECT_FALSE((isShiftedInt<1, 0>(0x8000000000000000)));
474 EXPECT_TRUE((isShiftedInt<1, 63>(0x8000000000000000)));
475 EXPECT_TRUE((isShiftedInt<2, 62>(0xC000000000000000)));
476 EXPECT_FALSE((isShiftedInt<2, 62>(0xE000000000000000)));
479 EXPECT_TRUE((isShiftedInt<11, 5>(int64_t(0x201) << 5)));
480 EXPECT_FALSE((isShiftedInt<11, 5>(int64_t(0x201) << 3)));
481 EXPECT_FALSE((isShiftedInt<11, 5>(int64_t(0x201) << 6)));
482 EXPECT_TRUE((isShiftedInt<11, 5>(-(int64_t(0x201) << 5))));
483 EXPECT_FALSE((isShiftedInt<11, 5>(-(int64_t(0x201) << 3))));
484 EXPECT_FALSE((isShiftedInt<11, 5>(-(int64_t(0x201) << 6))));
486 EXPECT_TRUE((isShiftedInt<6, 10>(-(int64_t(1) << 15))));
487 EXPECT_FALSE((isShiftedInt<6, 10>(int64_t(1) << 15)));