|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp 1324 int64_t Addend = Value.Addend + SignExtend32<16>(Opcode & 0x0000ffff);
1349 Value.Addend += SignExtend32<18>((Opcode & 0x0000ffff) << 2);
1351 Value.Addend += SignExtend32<21>((Opcode & 0x0007ffff) << 2);
1353 Value.Addend += SignExtend32<23>((Opcode & 0x001fffff) << 2);
1355 Value.Addend += SignExtend32<28>((Opcode & 0x03ffffff) << 2);
lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOARM.h 74 return SignExtend32<26>(Temp << 2);
lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp 134 O << formatDec(SignExtend32<12>(MI->getOperand(OpNo).getImm()));
136 O << formatDec(SignExtend32<13>(MI->getOperand(OpNo).getImm()));
lib/Target/ARC/Disassembler/ARCDisassembler.cpp 165 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(S9)));
192 DecodeSymbolicOperandOff(Inst, Address, SignExtend32<B>(InsnS), Decoder);
203 SignExtend32<B>(maskTrailingOnes<decltype(InsnS)>(B) & InsnS)));
lib/Target/ARM/Disassembler/ARMDisassembler.cpp 2619 int imm32 = SignExtend32<25>(tmp << 1);
2638 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2640 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2644 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2646 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
3654 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3656 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
3662 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3664 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
4474 int imm32 = SignExtend32<25>(tmp << 1);
4591 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
4593 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
4613 int imm32 = SignExtend32<25>(tmp << 1);
5596 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val)));
5923 DecVal = SignExtend32<size + 1>(Val << 1);
lib/Target/BPF/Disassembler/BPFDisassembler.cpp 132 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset)));
lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp 180 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset)));
204 Inst.addOperand(MCOperand::createImm(SignExtend32<10>(Offset)));
229 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset)));
lib/Target/Mips/Disassembler/MipsDisassembler.cpp 1524 int Offset = SignExtend32<16>(Insn & 0xffff);
1546 int Offset = SignExtend32<9>(Insn >> 7);
1567 int Offset = SignExtend32<16>(Insn & 0xffff);
1585 int Offset = SignExtend32<16>(Insn & 0xffff);
1602 int Offset = SignExtend32<12>(Insn & 0xfff);
1619 int Offset = SignExtend32<9>(Insn & 0x1ff);
1636 int Offset = SignExtend32<9>(Insn >> 7);
1653 int Offset = SignExtend32<16>(Insn & 0xffff);
1666 int Offset = SignExtend32<16>(Insn & 0xffff);
1681 int Immediate = SignExtend32<16>(Insn & 0xffff);
1694 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1839 Offset = SignExtend32<4>(Insn & 0xf);
1857 int Offset = SignExtend32<9>(Insn & 0x1ff);
1878 int Offset = SignExtend32<12>(Insn & 0x0fff);
1913 int Offset = SignExtend32<16>(Insn & 0xffff);
1931 int Offset = SignExtend32<16>(Insn & 0xffff);
1949 int Offset = SignExtend32<16>(Insn & 0xffff);
1967 int Offset = SignExtend32<16>(Insn & 0xffff);
1985 int Offset = SignExtend32<16>(Insn & 0xffff);
2003 int Offset = SignExtend32<11>(Insn & 0x07ff);
2019 int Offset = SignExtend32<11>(Insn & 0x07ff);
2202 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
2211 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2);
2229 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
2239 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
2249 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4;
2259 int32_t BranchOffset = SignExtend32<8>(Offset << 1);
2268 int32_t BranchOffset = SignExtend32<11>(Offset << 1);
2277 int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4;
2286 int32_t BranchOffset = SignExtend32<27>(Offset << 1);
2356 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy;
2370 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
2376 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
2382 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
2394 default: DecodedValue = SignExtend32<9>(Insn); break;
2533 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));
lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp 67 int32_t Offset = SignExtend32<24>(Imm);
lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp 338 Value = SignExtend32<5>(Value);
410 int32_t Imm = SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
421 O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
lib/Target/PowerPC/PPCISelLowering.cpp 2199 if (SignExtend32<5>(MaskVal) == MaskVal)
4753 SignExtend32<26>(Addr) != Addr)
lib/Target/Sparc/Disassembler/SparcDisassembler.cpp 383 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
524 unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
538 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
571 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
602 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
tools/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp 2047 imm32 = llvm::SignExtend32<25>(imm25);
2066 imm32 = llvm::SignExtend32<25>(imm25);
2076 imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2);
2083 imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2 |
2830 imm32 = llvm::SignExtend32<9>(Bits32(opcode, 7, 0) << 1);
2835 imm32 = llvm::SignExtend32<12>(Bits32(opcode, 10, 0) << 1);
2853 imm32 = llvm::SignExtend32<21>(imm21);
2868 imm32 = llvm::SignExtend32<25>(imm25);
2874 imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2);
tools/lldb/source/Plugins/Instruction/PPC64/EmulateInstructionPPC64.cpp 241 int32_t ids = llvm::SignExtend32<16>(ds << 2);
284 int32_t ids = llvm::SignExtend32<16>(ds << 2);
376 int32_t si_val = llvm::SignExtend32<16>(si);