reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AMDGPU/AMDGPUGenCallingConv.inc

  131       LocVT == MVT::v5f32) {

gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc

59166 /*129517*/        OPC_CheckChild0Type, MVT::v5f32,
62782 /*137031*/      OPC_CheckChild0Type, MVT::v5f32,
62819 /*137080*/      OPC_CheckType, MVT::v5f32,
77902 /*173206*/      /*SwitchType*/ 12, MVT::v5f32,// ->173220
77905                       MVT::v5f32, 3/*#Ops*/, 0, 1, 2, 
77947 /*173309*/      /*SwitchType*/ 12, MVT::v5f32,// ->173323
77950                       MVT::v5f32, 3/*#Ops*/, 0, 1, 2, 
77992 /*173412*/      /*SwitchType*/ 12, MVT::v5f32,// ->173426
77995                       MVT::v5f32, 3/*#Ops*/, 0, 1, 2, 
78025 /*173487*/      /*SwitchType*/ 12, MVT::v5f32,// ->173501
78028                       MVT::v5f32, 3/*#Ops*/, 0, 1, 2, 
78052 /*173547*/      OPC_SwitchType /*4 cases */, 12, MVT::v5f32,// ->173562
78055                       MVT::v5f32, 3/*#Ops*/, 0, 1, 2,

gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc

17473   /* 85 */ MVT::v5i32, MVT::v5f32, MVT::Other,

include/llvm/Support/MachineValueType.h

  521       case v5f32:
  615       case v5f32: return 5;
  770       case v5f32: return 160;
  977         if (NumElements == 5)    return MVT::v5f32;

lib/CodeGen/ValueTypes.cpp

  199   case MVT::v5f32:   return "v5f32";
  343   case MVT::v5f32:   return VectorType::get(Type::getFloatTy(Context), 5);

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

   82   setOperationAction(ISD::LOAD, MVT::v5f32, Promote);
   83   AddPromotedToType(ISD::LOAD, MVT::v5f32, MVT::v5i32);
  182   setOperationAction(ISD::STORE, MVT::v5f32, Promote);
  183   AddPromotedToType(ISD::STORE, MVT::v5f32, MVT::v5i32);
  283   setOperationAction(ISD::CONCAT_VECTORS, MVT::v5f32, Custom);
  292   setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5f32, Custom);
  399      MVT::v2f32, MVT::v3f32, MVT::v4f32, MVT::v5f32
  447   setOperationAction(ISD::SELECT, MVT::v5f32, Promote);
  448   AddPromotedToType(ISD::SELECT, MVT::v5f32, MVT::v5i32);

lib/Target/AMDGPU/SIISelLowering.cpp

  137   addRegisterClass(MVT::v5f32, &AMDGPU::VReg_160RegClass);
  333   setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5f32, Custom);

utils/TableGen/CodeGenTarget.cpp

  139   case MVT::v5f32:    return "MVT::v5f32";