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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenCallingConv.inc 115 LocVT == MVT::v3f32) {
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc36225 /* 76950*/ /*SwitchType*/ 37, MVT::v3f32,// ->76989
36235 MVT::v3f32, 9/*#Ops*/, 1, 2, 6, 7, 8, 9, 10, 11, 12,
36283 /* 77097*/ /*SwitchType*/ 38, MVT::v3f32,// ->77137
36293 MVT::v3f32, 10/*#Ops*/, 2, 1, 3, 7, 8, 9, 10, 11, 12, 13,
36344 /* 77253*/ /*SwitchType*/ 38, MVT::v3f32,// ->77293
36354 MVT::v3f32, 10/*#Ops*/, 2, 1, 3, 7, 8, 9, 10, 11, 12, 13,
36407 /* 77423*/ /*SwitchType*/ 58, MVT::v3f32,// ->77483
36422 MVT::v3f32, 10/*#Ops*/, 11, 1, 4, 12, 13, 14, 15, 16, 17, 18,
37261 /* 79362*/ OPC_CheckChild1Type, MVT::v3f32,
38787 /* 82879*/ /*SwitchType*/ 33, MVT::v3f32,// ->82914
38796 MVT::v3f32, 8/*#Ops*/, 1, 2, 5, 6, 7, 8, 9, 10,
38838 /* 83007*/ /*SwitchType*/ 34, MVT::v3f32,// ->83043
38847 MVT::v3f32, 9/*#Ops*/, 2, 1, 3, 6, 7, 8, 9, 10, 11,
38892 /* 83144*/ /*SwitchType*/ 34, MVT::v3f32,// ->83180
38901 MVT::v3f32, 9/*#Ops*/, 2, 1, 3, 6, 7, 8, 9, 10, 11,
38948 /* 83295*/ /*SwitchType*/ 54, MVT::v3f32,// ->83351
38962 MVT::v3f32, 9/*#Ops*/, 10, 1, 4, 11, 12, 13, 14, 15, 16,
40449 /* 87096*/ /*SwitchType*/ 33, MVT::v3f32,// ->87131
40458 MVT::v3f32, 8/*#Ops*/, 1, 2, 5, 6, 7, 8, 9, 10,
40524 /* 87296*/ /*SwitchType*/ 34, MVT::v3f32,// ->87332
40533 MVT::v3f32, 9/*#Ops*/, 2, 1, 3, 6, 7, 8, 9, 10, 11,
40602 /* 87505*/ /*SwitchType*/ 34, MVT::v3f32,// ->87541
40611 MVT::v3f32, 9/*#Ops*/, 2, 1, 3, 6, 7, 8, 9, 10, 11,
40692 /* 87768*/ /*SwitchType*/ 54, MVT::v3f32,// ->87824
40706 MVT::v3f32, 9/*#Ops*/, 10, 1, 4, 11, 12, 13, 14, 15, 16,
41674 /* 89965*/ OPC_CheckChild1Type, MVT::v3f32,
44146 /* 95529*/ OPC_CheckChild1Type, MVT::v3f32,
59142 /*129470*/ OPC_CheckChild0Type, MVT::v3f32,
62735 /*136968*/ OPC_CheckChild0Type, MVT::v3f32,
62813 /*137072*/ OPC_CheckType, MVT::v3f32,
77890 /*173178*/ /*SwitchType*/ 12, MVT::v3f32,// ->173192
77893 MVT::v3f32, 3/*#Ops*/, 0, 1, 2,
77935 /*173281*/ /*SwitchType*/ 12, MVT::v3f32,// ->173295
77938 MVT::v3f32, 3/*#Ops*/, 0, 1, 2,
77980 /*173384*/ /*SwitchType*/ 12, MVT::v3f32,// ->173398
77983 MVT::v3f32, 3/*#Ops*/, 0, 1, 2,
gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc17472 /* 82 */ MVT::v3i32, MVT::v3f32, MVT::Other,
include/llvm/Support/MachineValueType.h 519 case v3f32:
635 case v3f32: return 3;
749 case v3f32: return 96;
975 if (NumElements == 3) return MVT::v3f32;
lib/CodeGen/ValueTypes.cpp 197 case MVT::v3f32: return "v3f32";
341 case MVT::v3f32: return VectorType::get(Type::getFloatTy(Context), 3);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 76 setOperationAction(ISD::LOAD, MVT::v3f32, Promote);
77 AddPromotedToType(ISD::LOAD, MVT::v3f32, MVT::v3i32);
154 setLoadExtAction(ISD::EXTLOAD, MVT::v3f32, MVT::v3f16, Expand);
176 setOperationAction(ISD::STORE, MVT::v3f32, Promote);
177 AddPromotedToType(ISD::STORE, MVT::v3f32, MVT::v3i32);
218 setTruncStoreAction(MVT::v3f32, MVT::v3f16, Expand);
279 setOperationAction(ISD::CONCAT_VECTORS, MVT::v3f32, Custom);
288 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3f32, Custom);
399 MVT::v2f32, MVT::v3f32, MVT::v4f32, MVT::v5f32
441 setOperationAction(ISD::SELECT, MVT::v3f32, Promote);
442 AddPromotedToType(ISD::SELECT, MVT::v3f32, MVT::v3i32);
lib/Target/AMDGPU/SIISelLowering.cpp 128 addRegisterClass(MVT::v3f32, &AMDGPU::VReg_96RegClass);
327 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v3f32, Custom);
6718 (WidenedVT == MVT::v3i32 || WidenedVT == MVT::v3f32)) {
utils/TableGen/CodeGenTarget.cpp 137 case MVT::v3f32: return "MVT::v3f32";