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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/PowerPC/PPCGenCallingConv.inc 63 LocVT == MVT::v1i128 ||
520 LocVT == MVT::v1i128 ||
668 LocVT == MVT::v1i128 ||
774 LocVT == MVT::v1i128 ||
gen/lib/Target/PowerPC/PPCGenDAGISel.inc17430 MVT::v1i128, 3/*#Ops*/, 0, 1, 2,
17439 MVT::v1i128, 2/*#Ops*/, 0, 1,
17449 MVT::v1i128, 3/*#Ops*/, 0, 1, 2,
17459 MVT::v1i128, 3/*#Ops*/, 0, 1, 2,
17468 MVT::v1i128, 2/*#Ops*/, 0, 1,
17478 MVT::v1i128, 3/*#Ops*/, 0, 1, 2,
17652 MVT::v1i128, 1/*#Ops*/, 0,
18704 /* 47659*/ /*SwitchType*/ 19, MVT::v1i128,// ->47680
18710 MVT::v1i128, 2/*#Ops*/, 0, 1,
18764 /* 47791*/ /*SwitchType*/ 13, MVT::v1i128,// ->47806
18768 MVT::v1i128, 2/*#Ops*/, 0, 1,
18810 /* 47871*/ /*SwitchType*/ 5, MVT::v1i128,// ->47878
18849 /* 47936*/ /*SwitchType*/ 5, MVT::v1i128,// ->47943
18893 /* 48008*/ /*SwitchType*/ 5, MVT::v1i128,// ->48015
18937 /* 48080*/ /*SwitchType*/ 5, MVT::v1i128,// ->48087
18999 /* 48186*/ /*SwitchType*/ 5, MVT::v1i128,// ->48193
19058 /* 48299*/ OPC_CheckChild0Type, MVT::v1i128,
21189 /* 53129*/ OPC_CheckType, MVT::v1i128,
21192 MVT::v1i128, 2/*#Ops*/, 0, 1,
24360 /* 59021*/ /*SwitchType*/ 10, MVT::v1i128,// ->59033
24363 MVT::v1i128, 2/*#Ops*/, 0, 1,
27533 /* 66679*/ OPC_CheckChild1Type, MVT::v1i128,
27534 /* 66681*/ OPC_CheckType, MVT::v1i128,
27542 MVT::v1i128, 2/*#Ops*/, 2, 4,
27618 /* 66856*/ OPC_CheckChild1Type, MVT::v1i128,
27619 /* 66858*/ OPC_CheckType, MVT::v1i128,
27627 MVT::v1i128, 2/*#Ops*/, 2, 4,
28150 /* 67835*/ OPC_CheckChild1Type, MVT::v1i128,
28151 /* 67837*/ OPC_CheckType, MVT::v1i128,
28159 MVT::v1i128, 2/*#Ops*/, 2, 4,
28212 /* 67961*/ OPC_CheckChild1Type, MVT::v1i128,
28213 /* 67963*/ OPC_CheckType, MVT::v1i128,
28221 MVT::v1i128, 2/*#Ops*/, 2, 4,
42671 /*107036*/ /*SwitchType*/ 33, MVT::v1i128,// ->107071
42672 /*107038*/ OPC_CheckChild0Type, MVT::v1i128,
42681 MVT::v1i128, 2/*#Ops*/, 3, 4,
gen/lib/Target/PowerPC/PPCGenFastISel.inc 1793 if (RetVT.SimpleTy != MVT::v1i128)
1810 case MVT::v1i128: return fastEmit_ISD_ADD_MVT_v1i128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2797 if (RetVT.SimpleTy != MVT::v1i128)
2812 case MVT::v1i128: return fastEmit_ISD_SUB_MVT_v1i128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/PowerPC/PPCGenRegisterInfo.inc 3925 /* 12 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v1i128, MVT::v4f32, MVT::v2f64, MVT::f128, MVT::Other,
include/llvm/Support/MachineValueType.h 117 LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i128,
352 SimpleTy == MVT::v2i64 || SimpleTy == MVT::v1i128 ||
507 case v1i128: return i128;
657 case v1i128:
758 case v1i128:
962 if (NumElements == 1) return MVT::v1i128;
lib/CodeGen/ValueTypes.cpp 188 case MVT::v1i128: return "v1i128";
332 case MVT::v1i128: return VectorType::get(Type::getInt128Ty(Context), 1);
lib/Target/PowerPC/PPCISelLowering.cpp 587 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
597 if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128))
809 setOperationAction(ISD::SHL, MVT::v1i128, Expand);
810 setOperationAction(ISD::SRL, MVT::v1i128, Expand);
811 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
867 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
877 setOperationAction(ISD::SHL, MVT::v1i128, Legal);
878 setOperationAction(ISD::SRL, MVT::v1i128, Legal);
879 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
3302 ArgVT == MVT::v1i128 || ArgVT == MVT::f128)
3382 ArgVT == MVT::v1i128 || ArgVT == MVT::f128)
3993 case MVT::v1i128:
5778 case MVT::v1i128:
6159 case MVT::v1i128:
8998 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v1i128, V1);
8999 SDValue ReveQWord = DAG.getNode(PPCISD::XXREVERSE, dl, MVT::v1i128, Conv);
utils/TableGen/CodeGenTarget.cpp 128 case MVT::v1i128: return "MVT::v1i128";