reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/Hexagon/HexagonGenCallingConv.inc
  202         LocVT == MVT::v128i16 ||
  226         LocVT == MVT::v128i16 ||
  342         LocVT == MVT::v128i16 ||
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc
26009 /* 49936*/      /*SwitchType*/ 10, MVT::v128i16,// ->49948
26012                       MVT::v128i16, 2/*#Ops*/, 0, 1, 
26552 /* 50993*/      /*SwitchType*/ 10, MVT::v128i16,// ->51005
26555                       MVT::v128i16, 2/*#Ops*/, 0, 1, 
52251 /* 98537*/      /*SwitchType*/ 11, MVT::v128i16,// ->98550
52254                       MVT::v128i16, 3/*#Ops*/, 0, 1, 2, 
52550 /* 99199*/      /*SwitchType*/ 11, MVT::v128i16,// ->99212
52554                       MVT::v128i16, 1/*#Ops*/, 0, 
66972 /*128596*/      OPC_CheckChild0Type, MVT::v128i16,
66986 /*128617*/      OPC_SwitchType /*2 cases */, 5, MVT::v128i16,// ->128625
67004 /*128644*/      /*SwitchType*/ 5, MVT::v128i16,// ->128651
67229 /*129173*/    /*SwitchType*/ 11, MVT::v128i16,// ->129186
67233                     MVT::v128i16, 1/*#Ops*/, 0, 
69924 /*135424*/        OPC_SwitchType /*2 cases */, 56, MVT::v128i16,// ->135483
69940                         MVT::v128i16, 5/*#Ops*/, 1, 4, 5, 8, 9, 
70249 /*136258*/      OPC_CheckType, MVT::v128i16,
70263                     MVT::v128i16, 5/*#Ops*/, 1, 3, 4, 6, 7, 
70306 /*136381*/        OPC_CheckType, MVT::v128i16,
70309                       MVT::v128i16, 0/*#Ops*/, 
70397 /*136554*/      /*SwitchType*/ 25, MVT::v128i16,// ->136581
70405                       MVT::v128i16, 5/*#Ops*/, 2, 1, 3, 0, 4, 
71111 /*138225*/    /*SwitchType*/ 8, MVT::v128i16,// ->138235
71114                     MVT::v128i16, 0/*#Ops*/, 
71347 /*138747*/    /*SwitchType*/ 36, MVT::v128i16,// ->138785
71357                     MVT::v128i16, 5/*#Ops*/, 1, 2, 3, 4, 5, 
71684 /*139478*/      OPC_SwitchType /*2 cases */, 20, MVT::v128i16,// ->139501
71690                       MVT::v128i16, 1/*#Ops*/, 2, 
71709 /*139543*/      OPC_CheckChild0Type, MVT::v128i16,
71906 /*140024*/      OPC_SwitchType /*2 cases */, 20, MVT::v128i16,// ->140047
71912                       MVT::v128i16, 1/*#Ops*/, 2, 
71931 /*140089*/      OPC_CheckChild0Type, MVT::v128i16,
gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc
 2348   /* 41 */ MVT::v256i8, MVT::v128i16, MVT::v64i32, MVT::Other,
include/llvm/Support/MachineValueType.h
  382       return (SimpleTy == MVT::v256i8 || SimpleTy == MVT::v128i16 ||
  468       case v128i16:
  565       case v128i16:
  807       case v128i16:
  935         if (NumElements == 128) return MVT::v128i16;
lib/CodeGen/ValueTypes.cpp
  167   case MVT::v128i16: return "v128i16";
  311   case MVT::v128i16: return VectorType::get(Type::getInt16Ty(Context), 128);
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
   19 static const MVT LegalW128[] = { MVT::v256i8, MVT::v128i16, MVT::v64i32 };
   48     addRegisterClass(MVT::v128i16, &Hexagon::HvxWRRegClass);
utils/TableGen/CodeGenTarget.cpp
  107   case MVT::v128i16:  return "MVT::v128i16";