|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
include/llvm/MC/MCRegisterInfo.h 464 return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB);
lib/CodeGen/MachineCopyPropagation.cpp 161 !TRI.isSubRegisterEq(AvailCopy->getOperand(0).getReg(), Reg))
lib/MC/MCInstrDesc.cpp 57 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
62 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp 3970 if (RI->isSubRegisterEq(Rn, Rt))
3973 if (RI->isSubRegisterEq(Rn, Rt2))
4016 if (RI->isSubRegisterEq(Rn, Rt))
4019 if (RI->isSubRegisterEq(Rn, Rt2))
4048 if (RI->isSubRegisterEq(Rn, Rt))
4067 if (RI->isSubRegisterEq(Rn, Rt))
4083 if (RI->isSubRegisterEq(Rt, Rs) ||
4084 (RI->isSubRegisterEq(Rn, Rs) && Rn != AArch64::SP))
4097 if (RI->isSubRegisterEq(Rt1, Rs) || RI->isSubRegisterEq(Rt2, Rs) ||
4097 if (RI->isSubRegisterEq(Rt1, Rs) || RI->isSubRegisterEq(Rt2, Rs) ||
4098 (RI->isSubRegisterEq(Rn, Rs) && Rn != AArch64::SP))
lib/Target/AMDGPU/GCNNSAReassign.cpp 136 if (TRI->isSubRegisterEq(Reg, CSRegs[I]) &&
lib/Target/AMDGPU/GCNRegBankReassign.cpp 599 if (TRI->isSubRegisterEq(Reg, MaxReg))
606 if (TRI->isSubRegisterEq(Reg, CSRegs[I]) &&
lib/Target/AMDGPU/SIFrameLowering.cpp 486 bool CopyBufferFirst = TRI->isSubRegisterEq(PreloadedPrivateBufferReg,
lib/Target/X86/X86FixupBWInsts.cpp 262 if (MO.isUse() && !TRI->isSubRegisterEq(OrigDestReg, MO.getReg()) &&