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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Derived Classes
include/llvm/CodeGen/TargetRegisterInfo.h 228 class TargetRegisterInfo : public MCRegisterInfo {
Declarations
include/llvm/DebugInfo/DWARF/DWARFContext.h 46 class MCRegisterInfo;
include/llvm/DebugInfo/DWARF/DWARFDebugLoc.h 21 class MCRegisterInfo;
include/llvm/DebugInfo/DWARF/DWARFExpression.h 19 class MCRegisterInfo;
include/llvm/MC/MCContext.h 48 class MCRegisterInfo;
include/llvm/MC/MCInstPrinter.h 20 class MCRegisterInfo;
include/llvm/MC/MCInstrAnalysis.h 24 class MCRegisterInfo;
include/llvm/Support/TargetRegistry.h 49 class MCRegisterInfo;
include/llvm/Target/TargetMachine.h 33 class MCRegisterInfo;
lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h 27 class MCRegisterInfo;
lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h 28 class MCRegisterInfo;
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h 36 class MCRegisterInfo;
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h 30 class MCRegisterInfo;
lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.h 27 class MCRegisterInfo;
lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h 27 class MCRegisterInfo;
lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h 30 class MCRegisterInfo;
lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h 57 class MCRegisterInfo;
lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h 25 class MCRegisterInfo;
lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h 26 class MCRegisterInfo;
lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h 26 class MCRegisterInfo;
lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h 31 class MCRegisterInfo;
lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h 27 class MCRegisterInfo;
lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h 26 class MCRegisterInfo;
lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h 23 class MCRegisterInfo;
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h 28 class MCRegisterInfo;
tools/lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h 16 class MCRegisterInfo;
tools/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h 19 class MCRegisterInfo;
unittests/DebugInfo/DWARF/DwarfGenerator.h 38 class MCRegisterInfo;
References
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc 1114 extern const MCRegisterInfo::SubRegCoveredBits AArch64SubRegIdxRanges[] = {
3548 extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0Dwarf2L[] = {
3665 extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0Dwarf2L[] = {
3782 extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0L2Dwarf[] = {
4061 extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0L2Dwarf[] = {
4971 static inline void InitAArch64MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
20344 extern const MCRegisterInfo::SubRegCoveredBits AArch64SubRegIdxRanges[];
20347 extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0Dwarf2L[];
20350 extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0Dwarf2L[];
20353 extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0L2Dwarf[];
20356 extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0L2Dwarf[];
gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc 4726 extern const MCRegisterInfo::SubRegCoveredBits AMDGPUSubRegIdxRanges[] = {
11360 extern const MCRegisterInfo::DwarfLLVMRegPair AMDGPUDwarfFlavour0Dwarf2L[] = {
11757 extern const MCRegisterInfo::DwarfLLVMRegPair AMDGPUEHFlavour0Dwarf2L[] = {
12154 extern const MCRegisterInfo::DwarfLLVMRegPair AMDGPUDwarfFlavour0L2Dwarf[] = {
12865 extern const MCRegisterInfo::DwarfLLVMRegPair AMDGPUEHFlavour0L2Dwarf[] = {
17244 static inline void InitAMDGPUMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
48705 extern const MCRegisterInfo::SubRegCoveredBits AMDGPUSubRegIdxRanges[];
48708 extern const MCRegisterInfo::DwarfLLVMRegPair AMDGPUDwarfFlavour0Dwarf2L[];
48711 extern const MCRegisterInfo::DwarfLLVMRegPair AMDGPUEHFlavour0Dwarf2L[];
48714 extern const MCRegisterInfo::DwarfLLVMRegPair AMDGPUDwarfFlavour0L2Dwarf[];
48717 extern const MCRegisterInfo::DwarfLLVMRegPair AMDGPUEHFlavour0L2Dwarf[];
gen/lib/Target/AMDGPU/R600GenRegisterInfo.inc 1917 extern const MCRegisterInfo::SubRegCoveredBits R600SubRegIdxRanges[] = {
8759 static inline void InitR600MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
12349 extern const MCRegisterInfo::SubRegCoveredBits R600SubRegIdxRanges[];
gen/lib/Target/ARC/ARCGenRegisterInfo.inc 100 extern const MCRegisterInfo::SubRegCoveredBits ARCSubRegIdxRanges[] = {
270 extern const MCRegisterInfo::DwarfLLVMRegPair ARCDwarfFlavour0Dwarf2L[] = {
307 extern const MCRegisterInfo::DwarfLLVMRegPair ARCEHFlavour0Dwarf2L[] = {
344 extern const MCRegisterInfo::DwarfLLVMRegPair ARCDwarfFlavour0L2Dwarf[] = {
381 extern const MCRegisterInfo::DwarfLLVMRegPair ARCEHFlavour0L2Dwarf[] = {
454 static inline void InitARCMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
781 extern const MCRegisterInfo::SubRegCoveredBits ARCSubRegIdxRanges[];
784 extern const MCRegisterInfo::DwarfLLVMRegPair ARCDwarfFlavour0Dwarf2L[];
787 extern const MCRegisterInfo::DwarfLLVMRegPair ARCEHFlavour0Dwarf2L[];
790 extern const MCRegisterInfo::DwarfLLVMRegPair ARCDwarfFlavour0L2Dwarf[];
793 extern const MCRegisterInfo::DwarfLLVMRegPair ARCEHFlavour0L2Dwarf[];
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 973 extern const MCRegisterInfo::SubRegCoveredBits ARMSubRegIdxRanges[] = {
3016 extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0Dwarf2L[] = {
3068 extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0Dwarf2L[] = {
3120 extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0L2Dwarf[] = {
3173 extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0L2Dwarf[] = {
3523 static inline void InitARMMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
15939 extern const MCRegisterInfo::SubRegCoveredBits ARMSubRegIdxRanges[];
15942 extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0Dwarf2L[];
15945 extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0Dwarf2L[];
15948 extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0L2Dwarf[];
15951 extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0L2Dwarf[];
gen/lib/Target/AVR/AVRGenRegisterInfo.inc 194 extern const MCRegisterInfo::SubRegCoveredBits AVRSubRegIdxRanges[] = {
553 extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0Dwarf2L[] = {
592 extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0Dwarf2L[] = {
631 extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0L2Dwarf[] = {
687 extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0L2Dwarf[] = {
798 static inline void InitAVRMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
1681 extern const MCRegisterInfo::SubRegCoveredBits AVRSubRegIdxRanges[];
1684 extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0Dwarf2L[];
1687 extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0Dwarf2L[];
1690 extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0L2Dwarf[];
1693 extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0L2Dwarf[];
gen/lib/Target/BPF/BPFGenRegisterInfo.inc 104 extern const MCRegisterInfo::SubRegCoveredBits BPFSubRegIdxRanges[] = {
213 extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0Dwarf2L[] = {
229 extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0Dwarf2L[] = {
245 extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0L2Dwarf[] = {
273 extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0L2Dwarf[] = {
328 static inline void InitBPFMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
667 extern const MCRegisterInfo::SubRegCoveredBits BPFSubRegIdxRanges[];
670 extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0Dwarf2L[];
673 extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0Dwarf2L[];
676 extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0L2Dwarf[];
679 extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0L2Dwarf[];
gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc 465 extern const MCRegisterInfo::SubRegCoveredBits HexagonSubRegIdxRanges[] = {
1308 extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0Dwarf2L[] = {
1462 extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0Dwarf2L[] = {
1616 extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0L2Dwarf[] = {
1815 extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0L2Dwarf[] = {
2213 static inline void InitHexagonMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
3644 extern const MCRegisterInfo::SubRegCoveredBits HexagonSubRegIdxRanges[];
3647 extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0Dwarf2L[];
3650 extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0Dwarf2L[];
3653 extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0L2Dwarf[];
3656 extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0L2Dwarf[];
gen/lib/Target/Lanai/LanaiGenRegisterInfo.inc 136 extern const MCRegisterInfo::SubRegCoveredBits LanaiSubRegIdxRanges[] = {
308 extern const MCRegisterInfo::DwarfLLVMRegPair LanaiDwarfFlavour0Dwarf2L[] = {
344 extern const MCRegisterInfo::DwarfLLVMRegPair LanaiEHFlavour0Dwarf2L[] = {
380 extern const MCRegisterInfo::DwarfLLVMRegPair LanaiDwarfFlavour0L2Dwarf[] = {
423 extern const MCRegisterInfo::DwarfLLVMRegPair LanaiEHFlavour0L2Dwarf[] = {
509 static inline void InitLanaiMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
893 extern const MCRegisterInfo::SubRegCoveredBits LanaiSubRegIdxRanges[];
896 extern const MCRegisterInfo::DwarfLLVMRegPair LanaiDwarfFlavour0Dwarf2L[];
899 extern const MCRegisterInfo::DwarfLLVMRegPair LanaiEHFlavour0Dwarf2L[];
902 extern const MCRegisterInfo::DwarfLLVMRegPair LanaiDwarfFlavour0L2Dwarf[];
905 extern const MCRegisterInfo::DwarfLLVMRegPair LanaiEHFlavour0L2Dwarf[];
gen/lib/Target/MSP430/MSP430GenRegisterInfo.inc 118 extern const MCRegisterInfo::SubRegCoveredBits MSP430SubRegIdxRanges[] = {
281 static inline void InitMSP430MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
600 extern const MCRegisterInfo::SubRegCoveredBits MSP430SubRegIdxRanges[];
gen/lib/Target/Mips/MipsGenRegisterInfo.inc 690 extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[] = {
2747 extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[] = {
2823 extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[] = {
2899 extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[] = {
3103 extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[] = {
3751 static inline void InitMipsMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
7336 extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[];
7339 extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[];
7342 extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[];
7345 extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[];
7348 extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[];
gen/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc 171 extern const MCRegisterInfo::SubRegCoveredBits NVPTXSubRegIdxRanges[] = {
728 static inline void InitNVPTXMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
1301 extern const MCRegisterInfo::SubRegCoveredBits NVPTXSubRegIdxRanges[];
gen/lib/Target/PowerPC/PPCGenRegisterInfo.inc 497 extern const MCRegisterInfo::SubRegCoveredBits PPCSubRegIdxRanges[] = {
1745 extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour0Dwarf2L[] = {
1890 extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1Dwarf2L[] = {
2033 extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour0Dwarf2L[] = {
2178 extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour1Dwarf2L[] = {
2321 extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour0L2Dwarf[] = {
2599 extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1L2Dwarf[] = {
2874 extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour0L2Dwarf[] = {
3152 extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour1L2Dwarf[] = {
3773 static inline void InitPPCMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
5650 extern const MCRegisterInfo::SubRegCoveredBits PPCSubRegIdxRanges[];
5653 extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour0Dwarf2L[];
5656 extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1Dwarf2L[];
5659 extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour0Dwarf2L[];
5662 extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour1Dwarf2L[];
5665 extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour0L2Dwarf[];
5668 extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1L2Dwarf[];
5671 extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour0L2Dwarf[];
5674 extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour1L2Dwarf[];
gen/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc 127 const MCRegisterInfo &MRI = *Context.getRegisterInfo();
958 const MCRegisterInfo &MRI,
gen/lib/Target/RISCV/RISCVGenRegisterInfo.inc 197 extern const MCRegisterInfo::SubRegCoveredBits RISCVSubRegIdxRanges[] = {
621 extern const MCRegisterInfo::DwarfLLVMRegPair RISCVDwarfFlavour0Dwarf2L[] = {
689 extern const MCRegisterInfo::DwarfLLVMRegPair RISCVEHFlavour0Dwarf2L[] = {
757 extern const MCRegisterInfo::DwarfLLVMRegPair RISCVDwarfFlavour0L2Dwarf[] = {
857 extern const MCRegisterInfo::DwarfLLVMRegPair RISCVEHFlavour0L2Dwarf[] = {
1056 static inline void InitRISCVMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
1796 extern const MCRegisterInfo::SubRegCoveredBits RISCVSubRegIdxRanges[];
1799 extern const MCRegisterInfo::DwarfLLVMRegPair RISCVDwarfFlavour0Dwarf2L[];
1802 extern const MCRegisterInfo::DwarfLLVMRegPair RISCVEHFlavour0Dwarf2L[];
1805 extern const MCRegisterInfo::DwarfLLVMRegPair RISCVDwarfFlavour0L2Dwarf[];
1808 extern const MCRegisterInfo::DwarfLLVMRegPair RISCVEHFlavour0L2Dwarf[];
gen/lib/Target/Sparc/SparcGenRegisterInfo.inc 462 extern const MCRegisterInfo::SubRegCoveredBits SparcSubRegIdxRanges[] = {
1251 extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0Dwarf2L[] = {
1336 extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0Dwarf2L[] = {
1421 extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0L2Dwarf[] = {
1506 extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0L2Dwarf[] = {
1829 static inline void InitSparcMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
2761 extern const MCRegisterInfo::SubRegCoveredBits SparcSubRegIdxRanges[];
2764 extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0Dwarf2L[];
2767 extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0Dwarf2L[];
2770 extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0L2Dwarf[];
2773 extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0L2Dwarf[];
gen/lib/Target/SystemZ/SystemZGenRegisterInfo.inc 347 extern const MCRegisterInfo::SubRegCoveredBits SystemZSubRegIdxRanges[] = {
1126 extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0Dwarf2L[] = {
1210 extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0Dwarf2L[] = {
1294 extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0L2Dwarf[] = {
1410 extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0L2Dwarf[] = {
1723 static inline void InitSystemZMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
2927 extern const MCRegisterInfo::SubRegCoveredBits SystemZSubRegIdxRanges[];
2930 extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0Dwarf2L[];
2933 extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0Dwarf2L[];
2936 extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0L2Dwarf[];
2939 extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0L2Dwarf[];
gen/lib/Target/WebAssembly/WebAssemblyGenRegisterInfo.inc 81 extern const MCRegisterInfo::SubRegCoveredBits WebAssemblySubRegIdxRanges[] = {
227 static inline void InitWebAssemblyMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
554 extern const MCRegisterInfo::SubRegCoveredBits WebAssemblySubRegIdxRanges[];
gen/lib/Target/X86/X86GenRegisterInfo.inc 592 extern const MCRegisterInfo::SubRegCoveredBits X86SubRegIdxRanges[] = {
2711 extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0Dwarf2L[] = {
2788 extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1Dwarf2L[] = {
2833 extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2Dwarf2L[] = {
2878 extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0Dwarf2L[] = {
2955 extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1Dwarf2L[] = {
3000 extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2Dwarf2L[] = {
3045 extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0L2Dwarf[] = {
3195 extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1L2Dwarf[] = {
3345 extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2L2Dwarf[] = {
3495 extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0L2Dwarf[] = {
3645 extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1L2Dwarf[] = {
3795 extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2L2Dwarf[] = {
4229 static inline void InitX86MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
9886 extern const MCRegisterInfo::SubRegCoveredBits X86SubRegIdxRanges[];
9889 extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0Dwarf2L[];
9892 extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1Dwarf2L[];
9895 extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2Dwarf2L[];
9898 extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0Dwarf2L[];
9901 extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1Dwarf2L[];
9904 extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2Dwarf2L[];
9907 extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0L2Dwarf[];
9910 extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1L2Dwarf[];
9913 extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2L2Dwarf[];
9916 extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0L2Dwarf[];
9919 extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1L2Dwarf[];
9922 extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2L2Dwarf[];
gen/lib/Target/XCore/XCoreGenRegisterInfo.inc 81 extern const MCRegisterInfo::SubRegCoveredBits XCoreSubRegIdxRanges[] = {
176 extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0Dwarf2L[] = {
196 extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0Dwarf2L[] = {
216 extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0L2Dwarf[] = {
236 extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0L2Dwarf[] = {
275 static inline void InitXCoreMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
539 extern const MCRegisterInfo::SubRegCoveredBits XCoreSubRegIdxRanges[];
542 extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0Dwarf2L[];
545 extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0Dwarf2L[];
548 extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0L2Dwarf[];
551 extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0L2Dwarf[];
include/llvm/CodeGen/TargetRegisterInfo.h 228 class TargetRegisterInfo : public MCRegisterInfo {
include/llvm/DebugInfo/DWARF/DWARFContext.h 92 std::unique_ptr<MCRegisterInfo> RegInfo;
344 const MCRegisterInfo *getRegisterInfo() const { return RegInfo.get(); }
include/llvm/DebugInfo/DWARF/DWARFDebugFrame.h 74 void dump(raw_ostream &OS, const MCRegisterInfo *MRI, bool IsEH,
124 void printOperand(raw_ostream &OS, const MCRegisterInfo *MRI, bool IsEH,
149 virtual void dump(raw_ostream &OS, const MCRegisterInfo *MRI,
202 void dump(raw_ostream &OS, const MCRegisterInfo *MRI,
246 void dump(raw_ostream &OS, const MCRegisterInfo *MRI,
286 void dump(raw_ostream &OS, const MCRegisterInfo *MRI,
include/llvm/DebugInfo/DWARF/DWARFDebugLoc.h 45 unsigned AddressSize, const MCRegisterInfo *MRI, DWARFUnit *U,
63 void dump(raw_ostream &OS, const MCRegisterInfo *RegInfo, DIDumpOptions DumpOpts,
86 unsigned AddressSize, const MCRegisterInfo *MRI, DWARFUnit *U,
94 unsigned AddressSize, const MCRegisterInfo *RegInfo,
109 void dump(raw_ostream &OS, uint64_t BaseAddr, const MCRegisterInfo *RegInfo,
include/llvm/DebugInfo/DWARF/DWARFExpression.h 94 const MCRegisterInfo *RegInfo, DWARFUnit *U, bool isEH);
138 void print(raw_ostream &OS, const MCRegisterInfo *RegInfo, DWARFUnit *U,
include/llvm/MC/MCContext.h 80 const MCRegisterInfo *MRI;
305 explicit MCContext(const MCAsmInfo *MAI, const MCRegisterInfo *MRI,
320 const MCRegisterInfo *getRegisterInfo() const { return MRI; }
include/llvm/MC/MCInstPrinter.h 47 const MCRegisterInfo &MRI;
63 const MCRegisterInfo &mri) : MAI(mai), MII(mii), MRI(mri) {}
include/llvm/MC/MCInstrAnalysis.h 86 virtual bool clearsSuperRegisters(const MCRegisterInfo &MRI,
include/llvm/MC/MCInstrDesc.h 321 bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const;
595 const MCRegisterInfo *MRI = nullptr) const;
622 const MCRegisterInfo &RI) const;
include/llvm/MC/MCRegisterInfo.h 477 class MCSubRegIterator : public MCRegisterInfo::DiffListIterator {
479 MCSubRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI,
497 MCSubRegIndexIterator(MCRegister Reg, const MCRegisterInfo *MCRI)
524 class MCSuperRegIterator : public MCRegisterInfo::DiffListIterator {
528 MCSuperRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI,
560 class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator {
566 MCRegUnitIterator(MCRegister Reg, const MCRegisterInfo *MCRI) {
597 MCRegUnitMaskIterator(MCRegister Reg, const MCRegisterInfo *MCRI)
635 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) {
665 const MCRegisterInfo *MCRI;
673 MCRegAliasIterator(MCRegister Reg, const MCRegisterInfo *MCRI,
include/llvm/MCA/Context.h 52 const MCRegisterInfo &MRI;
56 Context(const MCRegisterInfo &R, const MCSubtargetInfo &S) : MRI(R), STI(S) {}
60 const MCRegisterInfo &getMCRegisterInfo() const { return MRI; }
include/llvm/MCA/HardwareUnits/RegisterFile.h 37 const MCRegisterInfo &MRI;
188 RegisterFile(const MCSchedModel &SM, const MCRegisterInfo &mri,
include/llvm/MCA/InstrBuilder.h 41 const MCRegisterInfo &MRI;
63 const MCRegisterInfo &RI, const MCInstrAnalysis *IA);
include/llvm/MCA/Stages/DispatchStage.h 69 DispatchStage(const MCSubtargetInfo &Subtarget, const MCRegisterInfo &MRI,
include/llvm/Support/TargetRegistry.h 130 using MCAsmInfoCtorFnTy = MCAsmInfo *(*)(const MCRegisterInfo &MRI,
135 using MCRegInfoCtorFnTy = MCRegisterInfo *(*)(const Triple &TT);
150 const MCRegisterInfo &MRI,
162 const MCRegisterInfo &MRI);
164 const MCRegisterInfo &MRI,
339 MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI, StringRef TheTriple,
364 MCRegisterInfo *createMCRegInfo(StringRef TT) const {
408 const MCRegisterInfo &MRI,
447 const MCRegisterInfo &MRI) const {
455 const MCRegisterInfo &MRI,
952 static MCAsmInfo *Allocator(const MCRegisterInfo & /*MRI*/, const Triple &TT,
1050 static MCRegisterInfo *Allocator(const Triple & /*TT*/) {
1139 const MCRegisterInfo &MRI,
1201 const MCRegisterInfo & /*MRI*/,
include/llvm/Target/TargetMachine.h 94 std::unique_ptr<const MCRegisterInfo> MRI;
191 const MCRegisterInfo *getMCRegisterInfo() const { return MRI.get(); }
lib/CodeGen/LLVMTargetMachine.cpp 126 const MCRegisterInfo &MRI = *getMCRegisterInfo();
245 const MCRegisterInfo &MRI = *getMCRegisterInfo();
lib/DebugInfo/DWARF/DWARFContext.cpp 290 const MCRegisterInfo *MRI,
lib/DebugInfo/DWARF/DWARFExpression.cpp 207 const MCRegisterInfo *MRI, bool isEH) {
237 const MCRegisterInfo *RegInfo,
287 void DWARFExpression::print(raw_ostream &OS, const MCRegisterInfo *RegInfo,
lib/MC/MCAsmStreamer.cpp 1537 const MCRegisterInfo *MRI = getContext().getRegisterInfo();
lib/MC/MCDisassembler/Disassembler.cpp 56 std::unique_ptr<const MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TT));
322 const MCRegisterInfo *MRI = DC->getRegisterInfo();
lib/MC/MCDisassembler/Disassembler.h 64 std::unique_ptr<const llvm::MCRegisterInfo> MRI;
90 std::unique_ptr<const MCRegisterInfo> &&MRI,
112 const MCRegisterInfo *getRegisterInfo() const { return MRI.get(); }
lib/MC/MCDwarf.cpp 1562 const MCRegisterInfo *MRI = context.getRegisterInfo();
lib/MC/MCInstrAnalysis.cpp 19 bool MCInstrAnalysis::clearsSuperRegisters(const MCRegisterInfo &MRI,
lib/MC/MCInstrDesc.cpp 33 const MCRegisterInfo &RI) const {
45 const MCRegisterInfo *MRI) const {
54 const MCRegisterInfo &RI) const {
lib/MCA/HardwareUnits/RegisterFile.cpp 25 RegisterFile::RegisterFile(const MCSchedModel &SM, const MCRegisterInfo &mri,
lib/MCA/InstrBuilder.cpp 29 const llvm::MCRegisterInfo &mri,
lib/MCA/Stages/DispatchStage.cpp 29 const MCRegisterInfo &MRI,
lib/Object/ModuleSymbolTable.cpp 82 std::unique_ptr<MCRegisterInfo> MRI(T->createMCRegInfo(TT.str()));
lib/Target/AArch64/AArch64FrameLowering.cpp 349 const MCRegisterInfo *MRI = STI.getRegisterInfo();
lib/Target/AArch64/AArch64ISelLowering.cpp 5546 const MCRegisterInfo *MRI = Subtarget->getRegisterInfo();
lib/Target/AArch64/AArch64InstrInfo.cpp 5582 const MCRegisterInfo *MRI = STI.getRegisterInfo();
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp 1434 const MCRegisterInfo *RI = Ctx.getRegisterInfo();
1446 const MCRegisterInfo *RI = Ctx.getRegisterInfo();
3890 const MCRegisterInfo *RI = getContext().getRegisterInfo();
5616 const MCRegisterInfo *RI = getContext().getRegisterInfo();
lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp 96 const MCRegisterInfo &MCRI = *Ctx.getRegisterInfo();
122 const MCRegisterInfo &MCRI = *Ctx.getRegisterInfo();
lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp 530 const MCRegisterInfo &MRI;
542 const MCRegisterInfo &MRI, bool IsILP32)
732 const MCRegisterInfo &MRI,
753 const MCRegisterInfo &MRI,
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp 46 const MCRegisterInfo &MRI)
51 const MCRegisterInfo &MRI)
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h 26 const MCRegisterInfo &MRI);
198 const MCRegisterInfo &MRI);
lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp 646 const MCRegisterInfo &MRI,
lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp 59 void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
233 static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) {
234 MCRegisterInfo *X = new MCRegisterInfo();
234 MCRegisterInfo *X = new MCRegisterInfo();
240 static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,
267 const MCRegisterInfo &MRI) {
lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h 40 const MCRegisterInfo &MRI,
44 const MCRegisterInfo &MRI,
48 const MCRegisterInfo &MRI,
69 void initLLVMToCVRegMapping(MCRegisterInfo *MRI);
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp 1048 bool subtargetHasRegister(const MCRegisterInfo &MRI, unsigned RegNo) const;
1205 const MCRegisterInfo *getMRI() const {
2133 const MCRegisterInfo *TRI = getContext().getRegisterInfo();
2264 const MCRegisterInfo *TRI = getContext().getRegisterInfo();
2803 const MCRegisterInfo *TRI = getContext().getRegisterInfo();
2899 const MCRegisterInfo *TRI = getContext().getRegisterInfo();
4343 bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h 43 const MCRegisterInfo &MRI;
lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp 236 const MCRegisterInfo &MRI,
lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp 284 const MCRegisterInfo &MRI) {
lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h 22 const MCInstrInfo &MII, const MCRegisterInfo &MRI)
33 const MCRegisterInfo &MRI);
240 const MCRegisterInfo &MRI)
lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp 59 static MCRegisterInfo *createAMDGPUMCRegisterInfo(const Triple &TT) {
60 MCRegisterInfo *X = new MCRegisterInfo();
60 MCRegisterInfo *X = new MCRegisterInfo();
79 const MCRegisterInfo &MRI) {
lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h 37 const MCRegisterInfo &MRI,
42 const MCRegisterInfo &MRI,
47 const MCRegisterInfo &MRI,
lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp 38 const MCRegisterInfo &MRI;
42 R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri)
94 const MCRegisterInfo &MRI,
lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp 45 const MCRegisterInfo &MRI;
52 SIMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
90 const MCRegisterInfo &MRI,
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp 957 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI) {
964 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI) {
1132 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h 546 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
549 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
575 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
lib/Target/ARC/ARCFrameLowering.cpp 122 const MCRegisterInfo *MRI = Context.getRegisterInfo();
lib/Target/ARC/MCTargetDesc/ARCInstPrinter.h 25 const MCRegisterInfo &MRI)
lib/Target/ARC/MCTargetDesc/ARCMCTargetDesc.cpp 43 static MCRegisterInfo *createARCMCRegisterInfo(const Triple &TT) {
44 auto *X = new MCRegisterInfo();
44 auto *X = new MCRegisterInfo();
54 static MCAsmInfo *createARCMCAsmInfo(const MCRegisterInfo &MRI,
70 const MCRegisterInfo &MRI) {
lib/Target/ARM/ARMBaseRegisterInfo.cpp 292 static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) {
lib/Target/ARM/ARMFrameLowering.cpp 364 const MCRegisterInfo *MRI = Context.getRegisterInfo();
2262 const MCRegisterInfo *MRI = Context.getRegisterInfo();
lib/Target/ARM/AsmParser/ARMAsmParser.cpp 185 const MCRegisterInfo *MRI;
lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp 1311 const MCRegisterInfo &MRI,
1334 const MCRegisterInfo &MRI,
1341 const MCRegisterInfo &MRI,
lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h 18 const MCRegisterInfo &MRI;
22 const MCRegisterInfo &MRI, MachO::CPUSubTypeARM st)
lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp 1339 const MCRegisterInfo *MRI = getContext().getRegisterInfo();
1432 const MCRegisterInfo *MRI = getContext().getRegisterInfo();
1450 const MCRegisterInfo *MRI = getContext().getRegisterInfo();
lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp 72 const MCRegisterInfo &MRI)
lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h 24 const MCRegisterInfo &MRI);
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp 1740 const MCRegisterInfo &MRI = *CTX.getRegisterInfo();
2010 const MCRegisterInfo &MRI,
2016 const MCRegisterInfo &MRI,
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp 183 static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) {
184 MCRegisterInfo *X = new MCRegisterInfo();
184 MCRegisterInfo *X = new MCRegisterInfo();
189 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI,
231 const MCRegisterInfo &MRI) {
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h 60 const MCRegisterInfo &MRI,
64 const MCRegisterInfo &MRI,
68 const MCRegisterInfo &MRI,
72 const MCRegisterInfo &MRI,
lib/Target/ARM/Thumb1FrameLowering.cpp 151 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
lib/Target/AVR/AVRAsmPrinter.cpp 57 const MCRegisterInfo &MRI;
lib/Target/AVR/AsmParser/AVRAsmParser.cpp 44 const MCRegisterInfo *MRI;
lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp 89 MCRegisterInfo const &MRI) {
lib/Target/AVR/MCTargetDesc/AVRInstPrinter.h 26 const MCRegisterInfo &MRI)
30 MCRegisterInfo const &MRI);
lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp 297 const MCRegisterInfo &MRI,
lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.cpp 47 static MCRegisterInfo *createAVRMCRegisterInfo(const Triple &TT) {
48 MCRegisterInfo *X = new MCRegisterInfo();
48 MCRegisterInfo *X = new MCRegisterInfo();
63 const MCRegisterInfo &MRI) {
lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.h 39 const MCRegisterInfo &MRI,
44 const MCRegisterInfo &MRI,
lib/Target/BPF/MCTargetDesc/BPFInstPrinter.h 22 const MCRegisterInfo &MRI)
lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp 34 const MCRegisterInfo &MRI;
38 BPFMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
75 const MCRegisterInfo &MRI,
81 const MCRegisterInfo &MRI,
lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp 41 static MCRegisterInfo *createBPFMCRegisterInfo(const Triple &TT) {
42 MCRegisterInfo *X = new MCRegisterInfo();
42 MCRegisterInfo *X = new MCRegisterInfo();
65 const MCRegisterInfo &MRI) {
lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h 37 const MCRegisterInfo &MRI,
40 const MCRegisterInfo &MRI,
44 const MCRegisterInfo &MRI,
47 const MCRegisterInfo &MRI,
lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp 471 const MCRegisterInfo *RI = getContext().getRegisterInfo();
1285 const MCRegisterInfo *RI = getContext().getRegisterInfo();
lib/Target/Hexagon/HexagonAsmPrinter.cpp 67 const MCRegisterInfo *RI) {
268 const MCRegisterInfo *RI = OutStreamer->getContext().getRegisterInfo();
lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp 767 MCRegisterInfo const & /*MRI*/,
lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h 28 MCRegisterInfo const &MRI)
lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp 193 MCRegisterInfo const &ri, bool ReportErrors)
lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h 37 const MCRegisterInfo &RI;
113 const MCRegisterInfo &ri, bool ReportErrors = true);
lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp 795 MCRegisterInfo const &MRI,
lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp 215 static MCRegisterInfo *createHexagonMCRegisterInfo(const Triple &TT) {
216 MCRegisterInfo *X = new MCRegisterInfo();
216 MCRegisterInfo *X = new MCRegisterInfo();
221 static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI,
239 const MCRegisterInfo &MRI)
lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h 71 MCRegisterInfo *createHexagonMCRegisterInfo(StringRef TT);
85 const MCRegisterInfo &MRI,
90 const MCRegisterInfo &MRI,
lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp 170 const MCRegisterInfo & /*MRI*/,
lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.h 24 const MCRegisterInfo &MRI)
lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp 307 const MCRegisterInfo & /*MRI*/,
lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp 47 static MCRegisterInfo *createLanaiMCRegisterInfo(const Triple & /*TT*/) {
48 MCRegisterInfo *X = new MCRegisterInfo();
48 MCRegisterInfo *X = new MCRegisterInfo();
78 const MCRegisterInfo &MRI) {
lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h 35 const MCRegisterInfo &MRI,
39 const MCRegisterInfo &MRI,
lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp 41 const MCRegisterInfo *MRI;
lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.h 22 const MCRegisterInfo &MRI)
lib/Target/MSP430/MCTargetDesc/MSP430MCCodeEmitter.cpp 203 const MCRegisterInfo &MRI,
lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp 39 static MCRegisterInfo *createMSP430MCRegisterInfo(const Triple &TT) {
40 MCRegisterInfo *X = new MCRegisterInfo();
40 MCRegisterInfo *X = new MCRegisterInfo();
54 const MCRegisterInfo &MRI) {
lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h 34 const MCRegisterInfo &MRI,
39 const MCRegisterInfo &MRI,
lib/Target/Mips/AsmParser/MipsAsmParser.cpp 821 const MCRegisterInfo *RegInfo;
850 const MCRegisterInfo *RegInfo,
1466 createNumericReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
1475 createGPRReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
1483 createFGRReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
1491 createHWRegsReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
1499 createFCCReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
1507 createACCReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
1515 createMSA128Reg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
1523 createMSACtrlReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
lib/Target/Mips/Disassembler/MipsDisassembler.cpp 581 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp 586 const MCRegisterInfo &MRI,
lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h 35 MipsAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT,
lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp 41 const MCRegisterInfo *MCRegInfo = Context.getRegisterInfo();
lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h 78 const MCRegisterInfo &MRI)
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp 45 const MCRegisterInfo &MRI,
51 const MCRegisterInfo &MRI,
lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp 71 static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) {
72 MCRegisterInfo *X = new MCRegisterInfo();
72 MCRegisterInfo *X = new MCRegisterInfo();
83 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
99 const MCRegisterInfo &MRI) {
lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h 36 const MCRegisterInfo &MRI,
39 const MCRegisterInfo &MRI,
43 const MCRegisterInfo &MRI,
lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp 74 const MCRegisterInfo *MCRegInfo) {
lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp 1124 const MCRegisterInfo *RegInfo = Context.getRegisterInfo();
lib/Target/Mips/Mips16FrameLowering.cpp 59 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
lib/Target/Mips/MipsOptionRecord.h 46 const MCRegisterInfo *TRI = Context.getRegisterInfo();
61 void SetPhysRegUsed(unsigned Reg, const MCRegisterInfo *MCRegInfo);
lib/Target/Mips/MipsSEFrameLowering.cpp 431 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp 31 const MCRegisterInfo &MRI)
lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h 25 const MCRegisterInfo &MRI);
lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp 40 static MCRegisterInfo *createNVPTXMCRegisterInfo(const Triple &TT) {
41 MCRegisterInfo *X = new MCRegisterInfo();
41 MCRegisterInfo *X = new MCRegisterInfo();
56 const MCRegisterInfo &MRI) {
lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp 258 const MCRegisterInfo &MRI,
lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h 31 const MCRegisterInfo &MRI, Triple T)
lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp 37 const MCRegisterInfo &MRI,
lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp 62 static MCRegisterInfo *createPPCMCRegisterInfo(const Triple &TT) {
68 MCRegisterInfo *X = new MCRegisterInfo();
68 MCRegisterInfo *X = new MCRegisterInfo();
78 static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI,
285 const MCRegisterInfo &MRI) {
lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h 40 const MCRegisterInfo &MRI,
44 const MCRegisterInfo &MRI,
lib/Target/PowerPC/PPCFrameLowering.cpp 783 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp 371 const MCRegisterInfo &MRI,
lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h 25 const MCRegisterInfo &MRI)
lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp 87 const MCRegisterInfo &MRI,
lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp 47 static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) {
48 MCRegisterInfo *X = new MCRegisterInfo();
48 MCRegisterInfo *X = new MCRegisterInfo();
53 static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI,
77 const MCRegisterInfo &MRI) {
lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h 36 const MCRegisterInfo &MRI,
40 const MCRegisterInfo &MRI,
lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h 23 const MCRegisterInfo &MRI)
lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp 230 const MCRegisterInfo &MRI,
lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp 35 static MCAsmInfo *createSparcMCAsmInfo(const MCRegisterInfo &MRI,
45 static MCAsmInfo *createSparcV9MCAsmInfo(const MCRegisterInfo &MRI,
61 static MCRegisterInfo *createSparcMCRegisterInfo(const Triple &TT) {
62 MCRegisterInfo *X = new MCRegisterInfo();
62 MCRegisterInfo *X = new MCRegisterInfo();
90 const MCRegisterInfo &MRI) {
lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h 36 const MCRegisterInfo &MRI,
39 const MCRegisterInfo &MRI,
lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.h 26 const MCRegisterInfo &MRI)
lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp 304 const MCRegisterInfo &MRI,
lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp 149 static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI,
167 static MCRegisterInfo *createSystemZMCRegisterInfo(const Triple &TT) {
168 MCRegisterInfo *X = new MCRegisterInfo();
168 MCRegisterInfo *X = new MCRegisterInfo();
182 const MCRegisterInfo &MRI) {
lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h 85 const MCRegisterInfo &MRI,
90 const MCRegisterInfo &MRI,
lib/Target/SystemZ/SystemZFrameLowering.cpp 350 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp 37 const MCRegisterInfo &MRI)
lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.h 37 const MCRegisterInfo &MRI);
lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp 37 static MCAsmInfo *createMCAsmInfo(const MCRegisterInfo & /*MRI*/,
49 static MCRegisterInfo *createMCRegisterInfo(const Triple & /*T*/) {
50 auto *X = new MCRegisterInfo();
50 auto *X = new MCRegisterInfo();
59 const MCRegisterInfo &MRI) {
65 const MCRegisterInfo & /*MRI*/,
72 const MCRegisterInfo & /*MRI*/,
lib/Target/X86/AsmParser/X86AsmParser.cpp 2874 const MCRegisterInfo *MRI = getContext().getRegisterInfo();
2940 const MCRegisterInfo *MRI = getContext().getRegisterInfo();
3750 const MCRegisterInfo *MRI = getContext().getRegisterInfo();
lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.h 23 const MCRegisterInfo &MRI)
lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp 487 const MCRegisterInfo &MRI;
787 DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI,
799 DarwinX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
820 DarwinX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
841 const MCRegisterInfo &MRI,
860 const MCRegisterInfo &MRI,
lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.h 23 using MCInstPrinter::MCInstPrinter;
lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.h 24 const MCRegisterInfo &MRI)
lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp 1651 const MCRegisterInfo &MRI,
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp 77 void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) {
313 static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) {
318 MCRegisterInfo *X = new MCRegisterInfo();
318 MCRegisterInfo *X = new MCRegisterInfo();
325 static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI,
373 const MCRegisterInfo &MRI) {
401 bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst,
415 bool X86MCInstrAnalysis::clearsSuperRegisters(const MCRegisterInfo &MRI,
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h 59 void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI);
72 const MCRegisterInfo &MRI,
77 const MCRegisterInfo &MRI,
81 const MCRegisterInfo &MRI,
lib/Target/X86/MCTargetDesc/X86WinCOFFTargetStreamer.cpp 290 static Printable printFPOReg(const MCRegisterInfo *MRI, unsigned LLVMReg) {
320 const MCRegisterInfo *MRI = OS.getContext().getRegisterInfo();
lib/Target/X86/X86FrameLowering.cpp 466 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
lib/Target/XCore/Disassembler/XCoreDisassembler.cpp 72 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.h 26 const MCRegisterInfo &MRI)
lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp 46 static MCRegisterInfo *createXCoreMCRegisterInfo(const Triple &TT) {
47 MCRegisterInfo *X = new MCRegisterInfo();
47 MCRegisterInfo *X = new MCRegisterInfo();
57 static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MRI,
73 const MCRegisterInfo &MRI) {
lib/Target/XCore/XCoreFrameLowering.cpp 229 const MCRegisterInfo *MRI = MMI->getContext().getRegisterInfo();
tools/clang/lib/Parse/ParseStmtAsm.cpp 584 std::unique_ptr<llvm::MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TT));
tools/clang/tools/driver/cc1as_main.cpp 353 std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(Opts.Triple));
tools/dsymutil/DwarfStreamer.h 150 std::unique_ptr<MCRegisterInfo> MRI;
tools/lldb/include/lldb/Target/ABI.h 127 llvm::MCRegisterInfo &GetMCRegisterInfo() { return *m_mc_register_info_up; }
141 ABI(lldb::ProcessSP process_sp, std::unique_ptr<llvm::MCRegisterInfo> info_up)
149 static std::unique_ptr<llvm::MCRegisterInfo>
153 std::unique_ptr<llvm::MCRegisterInfo> m_mc_register_info_up;
tools/lldb/source/Plugins/ABI/MacOSX-arm/ABIMacOSX_arm.h 89 std::unique_ptr<llvm::MCRegisterInfo> info_up)
tools/lldb/source/Plugins/ABI/MacOSX-arm64/ABIMacOSX_arm64.h 97 std::unique_ptr<llvm::MCRegisterInfo> info_up)
tools/lldb/source/Plugins/ABI/MacOSX-i386/ABIMacOSX_i386.h 96 std::unique_ptr<llvm::MCRegisterInfo> info_up)
tools/lldb/source/Plugins/ABI/SysV-arc/ABISysV_arc.h 100 using lldb_private::ABI::ABI; // Call CreateInstance instead.
tools/lldb/source/Plugins/ABI/SysV-arm/ABISysV_arm.h 89 std::unique_ptr<llvm::MCRegisterInfo> info_up)
tools/lldb/source/Plugins/ABI/SysV-arm64/ABISysV_arm64.h 96 std::unique_ptr<llvm::MCRegisterInfo> info_up)
tools/lldb/source/Plugins/ABI/SysV-hexagon/ABISysV_hexagon.h 101 std::unique_ptr<llvm::MCRegisterInfo> info_up)
tools/lldb/source/Plugins/ABI/SysV-i386/ABISysV_i386.h 104 std::unique_ptr<llvm::MCRegisterInfo> info_up)
tools/lldb/source/Plugins/ABI/SysV-mips/ABISysV_mips.h 91 std::unique_ptr<llvm::MCRegisterInfo> info_up)
tools/lldb/source/Plugins/ABI/SysV-mips64/ABISysV_mips64.h 104 std::unique_ptr<llvm::MCRegisterInfo> info_up)
tools/lldb/source/Plugins/ABI/SysV-ppc/ABISysV_ppc.h 100 std::unique_ptr<llvm::MCRegisterInfo> info_up)
tools/lldb/source/Plugins/ABI/SysV-ppc64/ABISysV_ppc64.h 100 std::unique_ptr<llvm::MCRegisterInfo> info_up)
tools/lldb/source/Plugins/ABI/SysV-s390x/ABISysV_s390x.h 92 std::unique_ptr<llvm::MCRegisterInfo> info_up)
tools/lldb/source/Plugins/ABI/SysV-x86_64/ABISysV_x86_64.h 102 std::unique_ptr<llvm::MCRegisterInfo> info_up)
tools/lldb/source/Plugins/ABI/Windows-x86_64/ABIWindows_x86_64.h 95 std::unique_ptr<llvm::MCRegisterInfo> info_up)
tools/lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp 65 std::unique_ptr<llvm::MCRegisterInfo> &®_info_up,
73 std::unique_ptr<llvm::MCRegisterInfo> m_reg_info_up;
943 std::unique_ptr<llvm::MCRegisterInfo> reg_info_up(
999 std::unique_ptr<llvm::MCRegisterInfo> &®_info_up,
tools/lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h 213 std::unique_ptr<llvm::MCRegisterInfo> m_reg_info;
tools/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h 176 std::unique_ptr<llvm::MCRegisterInfo> m_reg_info;
tools/lldb/source/Target/ABI.cpp 216 std::unique_ptr<llvm::MCRegisterInfo> ABI::MakeMCRegisterInfo(const ArchSpec &arch) {
227 std::unique_ptr<llvm::MCRegisterInfo> info_up(
tools/llvm-cfi-verify/lib/FileAnalysis.cpp 263 const MCRegisterInfo *FileAnalysis::getRegisterInfo() const {
tools/llvm-cfi-verify/lib/FileAnalysis.h 144 const MCRegisterInfo *getRegisterInfo() const;
206 std::unique_ptr<const MCRegisterInfo> RegisterInfo;
tools/llvm-dwp/llvm-dwp.cpp 675 std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName));
tools/llvm-exegesis/lib/Analysis.h 118 std::unique_ptr<MCRegisterInfo> RegInfo_;
tools/llvm-exegesis/lib/BenchmarkResult.cpp 51 generateRegNameToRegNoMapping(const MCRegisterInfo &RegInfo) {
tools/llvm-exegesis/lib/LlvmState.h 56 const MCRegisterInfo &getRegInfo() const {
tools/llvm-exegesis/lib/MCInstrDescView.cpp 226 void Instruction::dump(const MCRegisterInfo &RegInfo,
345 void DumpMCOperand(const MCRegisterInfo &MCRegisterInfo, const MCOperand &Op,
361 void DumpMCInst(const MCRegisterInfo &MCRegisterInfo,
tools/llvm-exegesis/lib/MCInstrDescView.h 132 void dump(const MCRegisterInfo &RegInfo,
204 void DumpMCInst(const MCRegisterInfo &MCRegisterInfo,
tools/llvm-exegesis/lib/RegisterAliasing.cpp 14 BitVector getAliasedBits(const MCRegisterInfo &RegInfo,
27 RegisterAliasingTracker::RegisterAliasingTracker(const MCRegisterInfo &RegInfo)
32 const MCRegisterInfo &RegInfo, const BitVector &ReservedReg,
41 RegisterAliasingTracker::RegisterAliasingTracker(const MCRegisterInfo &RegInfo,
49 const MCRegisterInfo &RegInfo, const BitVector &SourceBits) {
61 const MCRegisterInfo &RegInfo, const BitVector &ReservedReg)
tools/llvm-exegesis/lib/RegisterAliasing.h 28 BitVector getAliasedBits(const MCRegisterInfo &RegInfo,
43 RegisterAliasingTracker(const MCRegisterInfo &RegInfo,
48 RegisterAliasingTracker(const MCRegisterInfo &RegInfo,
64 RegisterAliasingTracker(const MCRegisterInfo &RegInfo);
67 void FillOriginAndAliasedBits(const MCRegisterInfo &RegInfo,
78 RegisterAliasingTrackerCache(const MCRegisterInfo &RegInfo,
88 const MCRegisterInfo ®Info() const { return RegInfo; }
97 const MCRegisterInfo &RegInfo;
tools/llvm-exegesis/lib/SnippetFile.cpp 31 const MCRegisterInfo *TheRegInfo,
111 const MCRegisterInfo *const RegInfo;
tools/llvm-exegesis/lib/X86/Target.cpp 209 const auto &RegInfo = State.getRegInfo();
tools/llvm-jitlink/llvm-jitlink.cpp 690 std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName));
tools/llvm-mc/Disassembler.cpp 139 std::unique_ptr<const MCRegisterInfo> MRI(T.createMCRegInfo(Triple));
tools/llvm-mc/llvm-mc.cpp 351 std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName));
tools/llvm-mca/llvm-mca.cpp 353 std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName));
tools/llvm-objdump/MachODump.cpp 7214 std::unique_ptr<const MCRegisterInfo> MRI(
7255 std::unique_ptr<const MCRegisterInfo> ThumbMRI;
tools/llvm-objdump/llvm-objdump.cpp 1536 std::unique_ptr<const MCRegisterInfo> MRI(
tools/llvm-rtdyld/llvm-rtdyld.cpp 749 std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName));
tools/sancov/sancov.cpp 717 std::unique_ptr<const MCRegisterInfo> MRI(
unittests/DebugInfo/DWARF/DwarfGenerator.h 238 std::unique_ptr<MCRegisterInfo> MRI;
unittests/ExecutionEngine/JITLink/JITLinkTestCommon.h 65 std::unique_ptr<MCRegisterInfo> MRI;
unittests/MC/DwarfLineTables.cpp 25 std::unique_ptr<MCRegisterInfo> MRI;
unittests/MC/MCInstPrinter.cpp 24 std::unique_ptr<MCRegisterInfo> MRI;
unittests/tools/llvm-exegesis/X86/RegisterAliasingTest.cpp 29 const auto &RegInfo = State.getRegInfo();
45 const auto &RegInfo = State.getRegInfo();
62 const auto &RegInfo = State.getRegInfo();
usr/include/c++/7.4.0/bits/move.h 72 constexpr _Tp&&
83 constexpr _Tp&&
usr/include/c++/7.4.0/bits/unique_ptr.h 68 default_delete(const default_delete<_Up>&) noexcept { }
72 operator()(_Tp* __ptr) const
74 static_assert(!is_void<_Tp>::value,
76 static_assert(sizeof(_Tp)>0,
122 using type = _Up*;
137 using pointer = typename _Ptr<_Tp, _Dp>::type;
161 typename __uniq_ptr_impl<_Tp, _Up>::_DeleterConstraint::type;
163 __uniq_ptr_impl<_Tp, _Dp> _M_t;
166 using pointer = typename __uniq_ptr_impl<_Tp, _Dp>::pointer;
167 using element_type = _Tp;
252 unique_ptr(unique_ptr<_Up, _Ep>&& __u) noexcept
297 __safe_conversion_up<_Up, _Ep>,
301 operator=(unique_ptr<_Up, _Ep>&& __u) noexcept
824 make_unique(_Args&&... __args)
usr/include/c++/7.4.0/type_traits 215 : public __is_void_helper<typename remove_cv<_Tp>::type>::type
581 : public __or_<is_lvalue_reference<_Tp>,
582 is_rvalue_reference<_Tp>>::type
601 : public __not_<__or_<is_function<_Tp>, is_reference<_Tp>,
601 : public __not_<__or_<is_function<_Tp>, is_reference<_Tp>,
602 is_void<_Tp>>>::type
638 : public __or_<is_object<_Tp>, is_reference<_Tp>>::type
638 : public __or_<is_object<_Tp>, is_reference<_Tp>>::type
1554 { typedef _Tp type; };
1558 { typedef _Tp type; };
1563 { typedef _Tp type; };
1574 remove_const<typename remove_volatile<_Tp>::type>::type type;
1645 { typedef _Tp& type; };
1650 : public __add_lvalue_reference_helper<_Tp>