reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Overridden By

lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

 1022   bool isReg() const override {

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

  242   bool isReg() const override {

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

 1274   bool isReg() const override { return Kind == k_Register; }

lib/Target/AVR/AsmParser/AVRAsmParser.cpp

  179   bool isReg() const { return Kind == k_Register; }

lib/Target/BPF/AsmParser/BPFAsmParser.cpp

  124   bool isReg() const override { return Kind == Register; }

lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp

  263   bool isReg() const override { return Kind == Register; }

lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp

  190   bool isReg() const override { return Kind == REGISTER; }

lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp

  157   bool isReg() const        { return Kind == k_Reg; }

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

 1240   bool isReg() const override {

lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp

  407   bool isReg() const override { return false; }

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

  256   bool isReg() const override { return Kind == KindTy::Register; }

lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

  256   bool isReg() const override { return Kind == k_Register; }

lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp

  219   bool isReg() const override {

lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp

   95   bool isReg() const override { return false; }

lib/Target/X86/AsmParser/X86Operand.h

  454   bool isReg() const override { return Kind == Register; }

References

gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc

12408         if (SrcOp1->isReg() && SrcOp2->isReg()) {
12408         if (SrcOp1->isReg() && SrcOp2->isReg()) {

gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc

10328         if (SrcOp1->isReg() && SrcOp2->isReg()) {
10328         if (SrcOp1->isReg() && SrcOp2->isReg()) {

gen/lib/Target/AVR/AVRGenAsmMatcher.inc

 1023         if (SrcOp1->isReg() && SrcOp2->isReg()) {
 1023         if (SrcOp1->isReg() && SrcOp2->isReg()) {

gen/lib/Target/BPF/BPFGenAsmMatcher.inc

  711         if (SrcOp1->isReg() && SrcOp2->isReg()) {
  711         if (SrcOp1->isReg() && SrcOp2->isReg()) {

gen/lib/Target/Hexagon/HexagonGenAsmMatcher.inc

 7494         if (SrcOp1->isReg() && SrcOp2->isReg()) {
 7494         if (SrcOp1->isReg() && SrcOp2->isReg()) {

gen/lib/Target/Lanai/LanaiGenAsmMatcher.inc

  877         if (SrcOp1->isReg() && SrcOp2->isReg()) {
  877         if (SrcOp1->isReg() && SrcOp2->isReg()) {

gen/lib/Target/MSP430/MSP430GenAsmMatcher.inc

  645         if (SrcOp1->isReg() && SrcOp2->isReg()) {
  645         if (SrcOp1->isReg() && SrcOp2->isReg()) {

gen/lib/Target/Mips/MipsGenAsmMatcher.inc

 4894         if (SrcOp1->isReg() && SrcOp2->isReg()) {
 4894         if (SrcOp1->isReg() && SrcOp2->isReg()) {

gen/lib/Target/PowerPC/PPCGenAsmMatcher.inc

 4133         if (SrcOp1->isReg() && SrcOp2->isReg()) {
 4133         if (SrcOp1->isReg() && SrcOp2->isReg()) {

gen/lib/Target/RISCV/RISCVGenAsmMatcher.inc

 1781         if (SrcOp1->isReg() && SrcOp2->isReg()) {
 1781         if (SrcOp1->isReg() && SrcOp2->isReg()) {

gen/lib/Target/Sparc/SparcGenAsmMatcher.inc

 2348         if (SrcOp1->isReg() && SrcOp2->isReg()) {
 2348         if (SrcOp1->isReg() && SrcOp2->isReg()) {

gen/lib/Target/SystemZ/SystemZGenAsmMatcher.inc

 2342         if (SrcOp1->isReg() && SrcOp2->isReg()) {
 2342         if (SrcOp1->isReg() && SrcOp2->isReg()) {

gen/lib/Target/WebAssembly/WebAssemblyGenAsmMatcher.inc

  399         if (SrcOp1->isReg() && SrcOp2->isReg()) {
  399         if (SrcOp1->isReg() && SrcOp2->isReg()) {

gen/lib/Target/X86/X86GenAsmMatcher.inc

 7590         if (SrcOp1->isReg() && SrcOp2->isReg()) {
 7590         if (SrcOp1->isReg() && SrcOp2->isReg()) {

include/llvm/MC/MCParser/MCTargetAsmParser.h

  463     assert(Op1.isReg() && Op2.isReg() && "Operands not all regs");
  463     assert(Op1.isReg() && Op2.isReg() && "Operands not all regs");

lib/MC/MCParser/AsmParser.cpp

 5820       if (Operand.isReg() && !Operand.needAddressOf() &&

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

 6658           ((*Operand).isReg() &&
 6673           (Operand->isReg() &&

lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp

 1113   else if (Operands[0]->isToken() && Operands[1]->isReg() &&
 1114            Operands[2]->isImm() && Operands[3]->isImm() && Operands[4]->isReg())
 1117            Operands[2]->isReg() && Operands[3]->isImm() &&
 1118            Operands[4]->isImm() && Operands[5]->isReg())
 1132   return Modifies && Operands[PossibleBaseIdx]->isReg() &&
 1133          Operands[PossibleDestIdx]->isReg() &&