reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/CodeGen/BreakFalseDeps.cpp
  200     e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
lib/CodeGen/DetectDeadLanes.cpp
  281   if (MI.getDesc().getNumDefs() != 1)
  429       assert(UseMI.getDesc().getNumDefs() == 1);
lib/CodeGen/ExecutionDomainFix.cpp
  239                 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
  259   for (unsigned i = mi->getDesc().getNumDefs(),
  271   for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) {
  290     for (unsigned i = mi->getDesc().getNumDefs(),
lib/CodeGen/GlobalISel/Localizer.cpp
  122     assert(MI.getDesc().getNumDefs() == 1 &&
lib/CodeGen/ImplicitNullChecks.cpp
  621   unsigned NumDefs = MI->getDesc().getNumDefs();
lib/CodeGen/LiveRangeEdit.cpp
  293       MI->getDesc().getNumDefs() == 1) {
lib/CodeGen/MachineInstr.cpp
  719   unsigned NumDefs = MCID->getNumDefs();
lib/CodeGen/MachineLICM.cpp
 1128   unsigned NumDefs = MI.getDesc().getNumDefs();
lib/CodeGen/MachineVerifier.cpp
 1596   unsigned NumDefs = MCID.getNumDefs();
 1663       if (MONum < MCID.getNumDefs()) {
lib/CodeGen/PeepholeOptimizer.cpp
  869     NumDefs = MI.getDesc().getNumDefs();
 1169   assert(MI.getDesc().getNumDefs() == 1 &&
 1315   if (MCID.getNumDefs() != 1)
 1336   if (MCID.getNumDefs() != 1)
 1517   if (MI.getDesc().getNumDefs() != 1)
 1756         for (unsigned i = MIDesc.getNumDefs(); i != MI->getNumOperands();
 1836   if (Def->getDesc().getNumDefs() != 1)
 2052            (DefIdx < Def->getDesc().getNumDefs() ||
lib/CodeGen/ReachingDefAnalysis.cpp
  103                 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
lib/CodeGen/RegAllocFast.cpp
 1082       (hasTiedOps && (hasPhysDefs || MCID.getNumDefs() > 1))) {
lib/CodeGen/RegisterCoalescer.cpp
 1239   if (MCID.getNumDefs() != 1)
lib/CodeGen/SelectionDAG/FastISel.cpp
 2052   Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
 2054   if (II.getNumDefs() >= 1)
 2074   Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
 2075   Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
 2077   if (II.getNumDefs() >= 1)
 2099   Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
 2100   Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
 2101   Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2);
 2103   if (II.getNumDefs() >= 1)
 2125   Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
 2127   if (II.getNumDefs() >= 1)
 2148   Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
 2150   if (II.getNumDefs() >= 1)
 2173   if (II.getNumDefs() >= 1)
 2192   Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
 2193   Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
 2195   if (II.getNumDefs() >= 1)
 2216   if (II.getNumDefs() >= 1)
lib/CodeGen/SelectionDAG/InstrEmitter.cpp
  134             if (i+II.getNumDefs() < II.getNumOperands()) {
  136                 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
  198   for (unsigned i = 0; i < II.getNumDefs(); ++i) {
  812   unsigned NumDefs = II.getNumDefs();
lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
  544       NodeNumDefs = std::min(N->getNumValues(), TID.getNumDefs());
lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
  434     NumRes = MCID.getNumDefs();
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
 1285     NumRes = MCID.getNumDefs();
 1418       for (unsigned i = 0; i < MCID.getNumDefs(); ++i)
 2114   unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
 2160   unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
 2289     unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs();
 2306     unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
 2820     unsigned NumRes = MCID.getNumDefs();
 2877   unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
 3065     unsigned NumRes = MCID.getNumDefs();
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
  127     if (ResNo >= II.getNumDefs() &&
  128         II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg)
  468         if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs())
  567   unsigned NRegDefs = SchedDAG->TII->get(Node->getMachineOpcode()).getNumDefs();
  654     OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs();
lib/CodeGen/TargetInstrInfo.cpp
  160   bool HasDef = MCID.getNumDefs();
  297   unsigned CommutableOpIdx1 = MCID.getNumDefs();
lib/CodeGen/TwoAddressInstructionPass.cpp
 1212   unsigned OtherOpIdx = MI->getDesc().getNumDefs();
 1358       if (UnfoldMCID.getNumDefs() == 1) {
lib/MC/MCParser/AsmParser.cpp
 5822         unsigned NumDefs = Desc.getNumDefs();
lib/MCA/InstrBuilder.cpp
  221   unsigned NumExplicitDefs = MCDesc.getNumDefs();
  295   unsigned NumExplicitDefs = MCDesc.getNumDefs();
  420   unsigned NumExplicitUses = MCDesc.getNumOperands() - MCDesc.getNumDefs();
  429   for (unsigned I = 0, OpIndex = MCDesc.getNumDefs(); I < NumExplicitUses;
lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
  142     for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) {
lib/Target/AArch64/AArch64FastISel.cpp
 1141       constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx));
 1143       constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1));
 1344   LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
 1345   RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
 1389   LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
 1431   LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
 1432   RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
 1476   LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
 1477   RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
 2171   SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs());
 2408   SrcReg = constrainOperandRegClass(II, SrcReg,  II.getNumDefs());
 2540     = constrainOperandRegClass(II, CondReg, II.getNumDefs());
 2558   AddrReg = constrainOperandRegClass(II, AddrReg,  II.getNumDefs());
 5114       II, getRegForValue(I->getPointerOperand()), II.getNumDefs());
 5116       II, getRegForValue(I->getCompareOperand()), II.getNumDefs() + 1);
 5118       II, getRegForValue(I->getNewValOperand()), II.getNumDefs() + 2);
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
  567     unsigned OpIdx = Desc.getNumDefs() + OpNo;
 2660           unsigned OpIdx = Desc.getNumDefs() + U.getOperandNo();
 2663             unsigned CommutedOpNo = CommuteIdx1 - Desc.getNumDefs();
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
 5914   for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
 5920     assert(Desc.getNumDefs() == 1);
 6201   for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
 6239   for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
 6683   for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
 6842   for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
lib/Target/ARM/ARMBaseInstrInfo.cpp
 3917   if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
 5199   assert(OpNum < MI.getDesc().getNumDefs() && "OpNum is not a def");
 5252   assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
 5279   assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
 5302   assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
lib/Target/ARM/ARMFastISel.cpp
  310   if (II.getNumDefs() >= 1) {
  335   if (II.getNumDefs() >= 1) {
  361   if (II.getNumDefs() >= 1) {
  383   if (II.getNumDefs() >= 1) {
lib/Target/ARM/ARMISelLowering.cpp
 1749   if (MCID.getNumDefs() == 0)
lib/Target/Hexagon/HexagonBitSimplify.cpp
 1314     unsigned NumD = MI->getDesc().getNumDefs();
lib/Target/Hexagon/HexagonInstrInfo.cpp
 2088   if (!ProdMI.getDesc().getNumDefs())
lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
   92   for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i)
  128   for (unsigned i = 0; i < MCID.getNumDefs(); ++i) {
  182     for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i)
  496     unsigned Defs = HexagonMCInstrInfo::getDesc(MCII, Inst).getNumDefs();
  513     for (unsigned j = HexagonMCInstrInfo::getDesc(MCII, I).getNumDefs(),
  531     for (unsigned J = 0, N = Desc.getNumDefs(); J < N; ++J)
lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
  821   for (auto I = Desc.getNumDefs(), N = Desc.getNumOperands(); I != N; ++I)
lib/Target/Mips/MipsFastISel.cpp
 2138     Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
 2139     Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
lib/Target/SystemZ/SystemZHazardRecognizer.cpp
  126     if (OpIdx >= MID.getNumDefs() &&
lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp
  215     else if (OpNo >= MII.get(MI->getOpcode()).getNumDefs())
  222     if (OpNo < MII.get(MI->getOpcode()).getNumDefs())
lib/Target/WebAssembly/WebAssemblyCallIndirectFixup.cpp
  130              make_range(MI.operands_begin() + MI.getDesc().getNumDefs() + 1,
  133         Ops.push_back(MI.getOperand(MI.getDesc().getNumDefs()));
  136         while (MI.getNumOperands() > MI.getDesc().getNumDefs())
lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
  271       assert(MI.getDesc().getNumDefs() <= 1);
  272       if (MI.getDesc().getNumDefs() == 1) {
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
  434         if (UseInst->getDesc().getNumDefs() == 0)
lib/Target/X86/MCTargetDesc/X86BaseInfo.h
  722     unsigned NumDefs = Desc.getNumDefs();
lib/Target/X86/MCTargetDesc/X86InstComments.cpp
  235   unsigned MaskOp = Desc.getNumDefs();
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
  419   unsigned NumDefs = Desc.getNumDefs();
lib/Target/X86/X86FastISel.cpp
 2075       if (II.getNumDefs()) {
 3983   Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
 3984   Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
 3985   Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2);
 3986   Op3 = constrainOperandRegClass(II, Op3, II.getNumDefs() + 3);
 3988   if (II.getNumDefs() >= 1)
lib/Target/X86/X86InstrInfo.cpp
 2149       unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
 2150       unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
 2153       if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
 4942       bool HasDef = MI.getDesc().getNumDefs();
 5663   if (MCID.getNumDefs() > 0) {
 5669     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
lib/Target/X86/X86SpeculativeLoadHardening.cpp
 1744             MI.getDesc().getNumDefs() == 1 && MI.getOperand(0).isReg() &&
 2207       if (UseMI.getDesc().getNumDefs() > 1)
tools/llvm-cfi-verify/lib/FileAnalysis.cpp
  350           for (unsigned i = InstrDesc.getNumDefs(),
tools/llvm-exegesis/lib/Assembler.cpp
  101       const bool IsDef = OpIndex < MCID.getNumDefs();
tools/llvm-exegesis/lib/MCInstrDescView.cpp
  106     Operand.IsDef = (OpIndex < Description->getNumDefs());