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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc 6857 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
6870 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
7101 { 254, 4, 1, 4, 817, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #254 = ADDWri
7102 { 255, 3, 1, 0, 560, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #255 = ADDWrr
7103 { 256, 4, 1, 4, 811, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #256 = ADDWrs
7105 { 258, 4, 1, 4, 817, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #258 = ADDXri
7106 { 259, 3, 1, 0, 561, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #259 = ADDXrr
7107 { 260, 4, 1, 4, 811, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #260 = ADDXrs
7122 { 275, 3, 1, 0, 6, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #275 = ADDlowTLS
7133 { 286, 2, 1, 4, 669, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #286 = ADR
7134 { 287, 2, 1, 4, 669, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #287 = ADRP
7172 { 325, 3, 1, 4, 714, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #325 = ANDWri
7173 { 326, 3, 1, 0, 712, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #326 = ANDWrr
7175 { 328, 3, 1, 4, 400, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #328 = ANDXri
7176 { 329, 3, 1, 0, 564, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #329 = ANDXrr
7252 { 405, 3, 1, 0, 715, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #405 = BICWrr
7254 { 407, 3, 1, 0, 566, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #407 = BICXrr
7671 { 824, 2, 1, 4, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #824 = DUPM_ZI
7672 { 825, 3, 1, 4, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #825 = DUP_ZI_B
7673 { 826, 3, 1, 4, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #826 = DUP_ZI_D
7674 { 827, 3, 1, 4, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #827 = DUP_ZI_H
7675 { 828, 3, 1, 4, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #828 = DUP_ZI_S
7700 { 853, 3, 1, 0, 717, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #853 = EONWrr
7702 { 855, 3, 1, 0, 568, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #855 = EONXrr
7719 { 872, 3, 1, 4, 719, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #872 = EORWri
7720 { 873, 3, 1, 0, 720, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #873 = EORWrr
7722 { 875, 3, 1, 4, 570, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #875 = EORXri
7723 { 876, 3, 1, 0, 571, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #876 = EORXrr
8189 { 1342, 2, 1, 4, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #1342 = FDUP_ZI_D
8190 { 1343, 2, 1, 4, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #1343 = FDUP_ZI_H
8191 { 1344, 2, 1, 4, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #1344 = FDUP_ZI_S
8391 { 1544, 1, 1, 0, 639, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #1544 = FMOVD0
8394 { 1547, 2, 1, 4, 636, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1547 = FMOVDi
8396 { 1549, 1, 1, 0, 15, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr }, // Inst #1549 = FMOVH0
8399 { 1552, 2, 1, 4, 839, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1552 = FMOVHi
8401 { 1554, 1, 1, 0, 639, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo179, -1 ,nullptr }, // Inst #1554 = FMOVS0
8403 { 1556, 2, 1, 4, 636, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1556 = FMOVSi
9523 { 2676, 2, 1, 0, 673, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2676 = LOADgot
9614 { 2767, 2, 1, 4, 591, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #2767 = MOVID
9615 { 2768, 2, 1, 4, 601, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #2768 = MOVIv16b_ns
9616 { 2769, 2, 1, 4, 601, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #2769 = MOVIv2d_ns
9617 { 2770, 3, 1, 4, 936, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo340, -1 ,nullptr }, // Inst #2770 = MOVIv2i32
9618 { 2771, 3, 1, 4, 936, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo340, -1 ,nullptr }, // Inst #2771 = MOVIv2s_msl
9619 { 2772, 3, 1, 4, 936, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo340, -1 ,nullptr }, // Inst #2772 = MOVIv4i16
9620 { 2773, 3, 1, 4, 601, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2773 = MOVIv4i32
9621 { 2774, 3, 1, 4, 601, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2774 = MOVIv4s_msl
9622 { 2775, 2, 1, 4, 936, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #2775 = MOVIv8b_ns
9623 { 2776, 3, 1, 4, 601, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2776 = MOVIv8i16
9640 { 2793, 3, 1, 0, 672, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2793 = MOVaddr
9641 { 2794, 3, 1, 0, 672, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2794 = MOVaddrBA
9642 { 2795, 3, 1, 0, 672, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2795 = MOVaddrCP
9643 { 2796, 3, 1, 0, 672, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2796 = MOVaddrEXT
9644 { 2797, 3, 1, 0, 672, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2797 = MOVaddrJT
9645 { 2798, 3, 1, 0, 672, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2798 = MOVaddrTLS
9647 { 2800, 2, 1, 0, 671, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #2800 = MOVi32imm
9648 { 2801, 2, 1, 0, 671, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2801 = MOVi64imm
9684 { 2837, 3, 1, 4, 774, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo340, -1 ,nullptr }, // Inst #2837 = MVNIv2i32
9685 { 2838, 3, 1, 4, 774, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo340, -1 ,nullptr }, // Inst #2838 = MVNIv2s_msl
9686 { 2839, 3, 1, 4, 774, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo340, -1 ,nullptr }, // Inst #2839 = MVNIv4i16
9687 { 2840, 3, 1, 4, 775, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2840 = MVNIv4i32
9688 { 2841, 3, 1, 4, 775, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2841 = MVNIv4s_msl
9689 { 2842, 3, 1, 4, 775, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2842 = MVNIv8i16
9716 { 2869, 3, 1, 0, 722, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #2869 = ORNWrr
9718 { 2871, 3, 1, 0, 573, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #2871 = ORNXrr
9724 { 2877, 3, 1, 4, 725, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #2877 = ORRWri
9725 { 2878, 3, 1, 0, 576, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #2878 = ORRWrr
9727 { 2880, 3, 1, 4, 575, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #2880 = ORRXri
9728 { 2881, 3, 1, 0, 401, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #2881 = ORRXrr
11283 { 4436, 4, 1, 4, 579, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #4436 = SUBWri
11284 { 4437, 3, 1, 0, 580, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4437 = SUBWrr
11285 { 4438, 4, 1, 4, 816, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #4438 = SUBWrs
11287 { 4440, 4, 1, 4, 579, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #4440 = SUBXri
11288 { 4441, 3, 1, 0, 580, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4441 = SUBXrr
11289 { 4442, 4, 1, 4, 816, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #4442 = SUBXrs
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc16072 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
16085 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
17659 { 1597, 1, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, ImplicitList2, ImplicitList6, OperandInfo147, -1 ,nullptr }, // Inst #1597 = SI_END_CF
17661 { 1599, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, ImplicitList1, OperandInfo149, -1 ,nullptr }, // Inst #1599 = SI_IF_BREAK
17676 { 1614, 1, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove), 0x1ULL, nullptr, ImplicitList10, OperandInfo161, -1 ,nullptr }, // Inst #1614 = SI_INIT_M0
18069 { 2007, 2, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x21ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #2007 = S_MOVK_I32
18075 { 2013, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x5ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #2013 = S_MOV_B32
18077 { 2015, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x5ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #2015 = S_MOV_B64
19927 { 3865, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3865 = V_MOV_B32_dpp
19928 { 3866, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3866 = V_MOV_B32_e32
19929 { 3867, 2, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3867 = V_MOV_B32_e64
19931 { 3869, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #3869 = V_MOV_B32_sdwa
gen/lib/Target/AMDGPU/R600GenInstrInfo.inc 648 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
661 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
gen/lib/Target/ARC/ARCGenInstrInfo.inc 653 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
666 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
1046 { 403, 2, 1, 4, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #403 = MOV_rs12
gen/lib/Target/ARM/ARMGenInstrInfo.inc 5843 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
5856 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
6048 { 215, 2, 1, 0, 451, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #215 = LDRLIT_ga_pcrel
6049 { 216, 2, 1, 0, 452, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #216 = LDRLIT_ga_pcrel_ldr
6067 { 234, 2, 1, 0, 332, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #234 = MOV_ga_pcrel
6068 { 235, 2, 1, 0, 333, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #235 = MOV_ga_pcrel_ldr
6070 { 237, 2, 1, 0, 331, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #237 = MOVi32imm
6252 { 419, 1, 1, 4, 1042, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #419 = VMOVD0
6254 { 421, 1, 1, 4, 991, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #421 = VMOVQ0
6361 { 528, 3, 1, 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #528 = t2LDRpci_pic
6363 { 530, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #530 = t2LEApcrel
6378 { 545, 2, 1, 0, 355, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #545 = t2MOV_ga_pcrel
6380 { 547, 2, 1, 0, 354, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #547 = t2MOVi32imm
6414 { 581, 3, 1, 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #581 = tLDRpci_pic
6415 { 582, 4, 1, 2, 38, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #582 = tLEApcrel
6435 { 602, 6, 1, 4, 690, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #602 = ADDri
6439 { 606, 4, 1, 4, 707, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xd01ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #606 = ADR
6444 { 611, 6, 1, 4, 321, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #611 = ANDri
6450 { 617, 6, 1, 4, 321, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #617 = BICri
6489 { 656, 6, 1, 4, 321, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #656 = EORri
6494 { 661, 4, 1, 4, 955, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x8c00ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #661 = FCONSTD
6495 { 662, 4, 1, 4, 956, 0|(1ULL<<MCID::Rematerializable), 0x8c00ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #662 = FCONSTH
6496 { 663, 4, 1, 4, 957, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x8c00ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr }, // Inst #663 = FCONSTS
6545 { 712, 5, 1, 4, 386, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x310ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #712 = LDRBi12
6546 { 713, 6, 1, 4, 387, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x300ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #713 = LDRBrs
6575 { 742, 5, 1, 4, 397, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x310ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #742 = LDRcp
6576 { 743, 5, 1, 4, 385, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x310ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #743 = LDRi12
6577 { 744, 6, 1, 4, 348, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x300ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #744 = LDRrs
6586 { 753, 5, 1, 4, 864, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0x2201ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #753 = MOVi
6587 { 754, 4, 1, 4, 864, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2201ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #754 = MOVi16
7030 { 1197, 5, 1, 4, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x140c80ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1197 = MVE_VMOVimmf32
7031 { 1198, 5, 1, 4, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x140c80ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1198 = MVE_VMOVimmi16
7032 { 1199, 5, 1, 4, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x140c80ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1199 = MVE_VMOVimmi32
7033 { 1200, 5, 1, 4, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove), 0x140c80ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1200 = MVE_VMOVimmi64
7034 { 1201, 5, 1, 4, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x140c80ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1201 = MVE_VMOVimmi8
7068 { 1235, 5, 1, 4, 0, 0|(1ULL<<MCID::Rematerializable), 0x140c80ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1235 = MVE_VMVNimmi16
7069 { 1236, 5, 1, 4, 0, 0|(1ULL<<MCID::Rematerializable), 0x140c80ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1236 = MVE_VMVNimmi32
7458 { 1625, 5, 1, 4, 708, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0x2201ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #1625 = MVNi
7470 { 1637, 6, 1, 4, 321, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #1637 = ORRri
7504 { 1671, 6, 1, 4, 690, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #1671 = RSBri
7650 { 1817, 6, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #1817 = SUBri
8467 { 2634, 5, 1, 4, 585, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x18b05ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #2634 = VLDRD
8468 { 2635, 5, 1, 4, 744, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x18b11ULL, nullptr, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #2635 = VLDRH
8469 { 2636, 5, 1, 4, 586, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x18b05ULL, nullptr, nullptr, OperandInfo363, -1 ,nullptr }, // Inst #2636 = VLDRS
8604 { 2771, 4, 1, 4, 564, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo382, -1 ,nullptr }, // Inst #2771 = VMOVv16i8
8605 { 2772, 4, 1, 4, 564, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #2772 = VMOVv1i64
8606 { 2773, 4, 1, 4, 564, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #2773 = VMOVv2f32
8607 { 2774, 4, 1, 4, 564, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #2774 = VMOVv2i32
8608 { 2775, 4, 1, 4, 564, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo382, -1 ,nullptr }, // Inst #2775 = VMOVv2i64
8609 { 2776, 4, 1, 4, 564, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo382, -1 ,nullptr }, // Inst #2776 = VMOVv4f32
8610 { 2777, 4, 1, 4, 564, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #2777 = VMOVv4i16
8611 { 2778, 4, 1, 4, 564, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo382, -1 ,nullptr }, // Inst #2778 = VMOVv4i32
8612 { 2779, 4, 1, 4, 564, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo382, -1 ,nullptr }, // Inst #2779 = VMOVv8i16
8613 { 2780, 4, 1, 4, 564, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #2780 = VMOVv8i8
8674 { 2841, 4, 1, 4, 964, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #2841 = VMVNv2i32
8675 { 2842, 4, 1, 4, 964, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #2842 = VMVNv4i16
8676 { 2843, 4, 1, 4, 964, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo382, -1 ,nullptr }, // Inst #2843 = VMVNv4i32
8677 { 2844, 4, 1, 4, 964, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo382, -1 ,nullptr }, // Inst #2844 = VMVNv8i16
9575 { 3742, 6, 1, 4, 690, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo450, -1 ,nullptr }, // Inst #3742 = t2ADDri
9670 { 3837, 4, 1, 4, 391, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #3837 = t2LDRBpci
9684 { 3851, 4, 1, 4, 391, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #3851 = t2LDRHpci
9691 { 3858, 4, 1, 4, 399, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #3858 = t2LDRSBpci
9698 { 3865, 4, 1, 4, 399, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #3865 = t2LDRSHpci
9703 { 3870, 5, 1, 4, 389, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8bULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #3870 = t2LDRi12
9704 { 3871, 5, 1, 4, 389, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8cULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #3871 = t2LDRi8
9705 { 3872, 4, 1, 4, 389, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #3872 = t2LDRpci
9706 { 3873, 6, 1, 4, 390, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8dULL, nullptr, nullptr, OperandInfo471, -1 ,nullptr }, // Inst #3873 = t2LDRs
9720 { 3887, 5, 1, 4, 679, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL, nullptr, nullptr, OperandInfo474, -1 ,nullptr }, // Inst #3887 = t2MOVi
9721 { 3888, 4, 1, 4, 679, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL, nullptr, nullptr, OperandInfo454, -1 ,nullptr }, // Inst #3888 = t2MOVi16
9737 { 3904, 5, 1, 4, 694, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL, nullptr, nullptr, OperandInfo474, -1 ,nullptr }, // Inst #3904 = t2MVNi
9900 { 4067, 6, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo450, -1 ,nullptr }, // Inst #4067 = t2SUBri
9995 { 4162, 5, 1, 2, 903, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc87ULL, nullptr, nullptr, OperandInfo512, -1 ,nullptr }, // Inst #4162 = tLDRBi
9996 { 4163, 5, 1, 2, 394, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc87ULL, nullptr, nullptr, OperandInfo513, -1 ,nullptr }, // Inst #4163 = tLDRBr
9997 { 4164, 5, 1, 2, 903, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc88ULL, nullptr, nullptr, OperandInfo512, -1 ,nullptr }, // Inst #4164 = tLDRHi
9998 { 4165, 5, 1, 2, 394, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc88ULL, nullptr, nullptr, OperandInfo513, -1 ,nullptr }, // Inst #4165 = tLDRHr
10001 { 4168, 5, 1, 2, 904, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc89ULL, nullptr, nullptr, OperandInfo512, -1 ,nullptr }, // Inst #4168 = tLDRi
10002 { 4169, 4, 1, 2, 904, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8aULL, nullptr, nullptr, OperandInfo505, -1 ,nullptr }, // Inst #4169 = tLDRpci
10003 { 4170, 5, 1, 2, 395, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc89ULL, nullptr, nullptr, OperandInfo513, -1 ,nullptr }, // Inst #4170 = tLDRr
gen/lib/Target/AVR/AVRGenInstrInfo.inc 493 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
506 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
686 { 203, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #203 = INWRdA
687 { 204, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #204 = LDDWRdPtrQ
688 { 205, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #205 = LDDWRdYQ
689 { 206, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #206 = LDIWRdK
690 { 207, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #207 = LDSWRdK
691 { 208, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #208 = LDWRdPtr
694 { 211, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList4, OperandInfo56, -1 ,nullptr }, // Inst #211 = LPMWRdZ
695 { 212, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList4, OperandInfo56, -1 ,nullptr }, // Inst #212 = LPMWRdZPi
772 { 289, 2, 1, 2, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #289 = INRdA
777 { 294, 3, 1, 2, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #294 = LDDRdPtrQ
778 { 295, 2, 1, 2, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #295 = LDIRdK
779 { 296, 2, 1, 2, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #296 = LDRdPtr
782 { 299, 2, 1, 4, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #299 = LDSRdK
783 { 300, 0, 0, 2, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList4, ImplicitList7, nullptr, -1 ,nullptr }, // Inst #300 = LPM
784 { 301, 2, 1, 2, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #301 = LPMRdZ
785 { 302, 2, 1, 2, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList4, OperandInfo78, -1 ,nullptr }, // Inst #302 = LPMRdZPi
gen/lib/Target/BPF/BPFGenInstrInfo.inc 430 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
443 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
677 { 257, 2, 1, 8, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #257 = LD_imm64
683 { 263, 2, 1, 8, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #263 = MOV_ri
684 { 264, 2, 1, 8, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #264 = MOV_ri_32
685 { 265, 2, 1, 8, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #265 = MOV_rr
686 { 266, 2, 1, 8, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #266 = MOV_rr_32
gen/lib/Target/Hexagon/HexagonGenInstrInfo.inc 3640 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
3653 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
3813 { 183, 2, 1, 4, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x3ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #183 = A2_tfrpi
3920 { 290, 1, 1, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #290 = PS_false
3921 { 291, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x214800029ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #291 = PS_fi
3922 { 292, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x216800029ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #292 = PS_fia
3936 { 306, 1, 1, 4, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x10ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #306 = PS_qfalse
3937 { 307, 1, 1, 4, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x10ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #307 = PS_qtrue
3950 { 320, 1, 1, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #320 = PS_true
3951 { 321, 1, 1, 4, 39, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x11ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #321 = PS_vdd0
4398 { 768, 3, 1, 4, 6, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x112800000ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #768 = A2_combineii
4479 { 849, 2, 1, 4, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x212808000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #849 = A2_tfrsi
4689 { 1059, 2, 1, 4, 29, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x25ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #1059 = CONST32
4690 { 1060, 2, 1, 4, 29, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x25ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #1060 = CONST64
4769 { 1139, 2, 1, 4, 6, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x8000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #1139 = HI
5177 { 1547, 2, 1, 4, 6, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x8000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #1547 = LO
5796 { 2166, 2, 1, 4, 69, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x802cULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #2166 = S2_vsplatrb
5797 { 2167, 2, 1, 4, 69, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2cULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #2167 = S2_vsplatrh
5800 { 2170, 2, 1, 4, 69, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2cULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #2170 = S2_vsxtbh
5801 { 2171, 2, 1, 4, 69, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2cULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #2171 = S2_vsxthw
5806 { 2176, 2, 1, 4, 69, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2cULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #2176 = S2_vzxtbh
5807 { 2177, 2, 1, 4, 69, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2cULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #2177 = S2_vzxthw
gen/lib/Target/Lanai/LanaiGenInstrInfo.inc 380 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
393 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
573 { 203, 2, 1, 4, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #203 = LDADDR
574 { 204, 4, 1, 4, 4, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #204 = LDBs_RI
576 { 206, 4, 1, 4, 4, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #206 = LDBz_RI
578 { 208, 4, 1, 4, 4, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #208 = LDHs_RI
580 { 210, 4, 1, 4, 4, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #210 = LDHz_RI
582 { 212, 4, 1, 4, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #212 = LDW_RI
591 { 221, 2, 1, 4, 1, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #221 = MOVHI
601 { 231, 3, 1, 4, 1, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo38, -1 ,nullptr }, // Inst #231 = SA_F_I
602 { 232, 3, 1, 4, 1, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #232 = SA_I
610 { 240, 2, 1, 4, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #240 = SLI
611 { 241, 3, 1, 4, 1, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo38, -1 ,nullptr }, // Inst #241 = SL_F_I
612 { 242, 3, 1, 4, 1, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #242 = SL_I
gen/lib/Target/MSP430/MSP430GenInstrInfo.inc 651 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
664 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
1025 { 384, 2, 1, 2, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #384 = MOV16rc
1026 { 385, 2, 1, 4, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #385 = MOV16ri
1027 { 386, 3, 1, 4, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #386 = MOV16rm
1028 { 387, 2, 1, 2, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #387 = MOV16rn
1036 { 395, 2, 1, 2, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #395 = MOV8rc
1037 { 396, 2, 1, 4, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #396 = MOV8ri
1038 { 397, 3, 1, 4, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #397 = MOV8rm
1039 { 398, 2, 1, 2, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #398 = MOV8rn
gen/lib/Target/Mips/MipsGenInstrInfo.inc 4825 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
4838 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
5407 { 592, 3, 1, 4, 491, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #592 = ADD
5415 { 600, 3, 1, 4, 767, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #600 = ADDIU_MMR6
5450 { 635, 3, 1, 4, 768, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #635 = ADDU_MMR6
5473 { 658, 3, 1, 4, 732, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #658 = ADD_MM
5474 { 659, 3, 1, 4, 769, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #659 = ADD_MMR6
5475 { 660, 3, 1, 4, 492, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #660 = ADDi
5476 { 661, 3, 1, 4, 733, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #661 = ADDi_MM
5477 { 662, 3, 1, 4, 493, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #662 = ADDiu
5478 { 663, 3, 1, 4, 730, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #663 = ADDiu_MM
5479 { 664, 3, 1, 4, 504, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #664 = ADDu
5480 { 665, 3, 1, 4, 731, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #665 = ADDu_MM
5485 { 670, 3, 1, 4, 359, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #670 = AND
5488 { 673, 3, 1, 4, 798, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #673 = AND64
5492 { 677, 3, 1, 4, 773, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #677 = ANDI_MMR6
5493 { 678, 3, 1, 4, 734, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #678 = AND_MM
5494 { 679, 3, 1, 4, 772, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #679 = AND_MMR6
5496 { 681, 3, 1, 4, 494, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #681 = ANDi
5497 { 682, 3, 1, 4, 798, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #682 = ANDi64
5498 { 683, 3, 1, 4, 735, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #683 = ANDi_MM
5531 { 716, 3, 1, 2, 727, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #716 = AddiuRxRxImm16
5532 { 717, 3, 1, 4, 727, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #717 = AddiuRxRxImmX16
5536 { 721, 3, 1, 2, 727, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #721 = AdduRxRyRz16
5537 { 722, 3, 1, 2, 727, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #722 = AndRxRxRy16
5539 { 724, 3, 1, 4, 1190, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #724 = BADDu
6053 { 1238, 3, 1, 4, 808, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1238 = DADD
6054 { 1239, 3, 1, 4, 809, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #1239 = DADDi
6055 { 1240, 3, 1, 4, 810, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #1240 = DADDiu
6056 { 1241, 3, 1, 4, 811, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1241 = DADDu
6081 { 1266, 3, 1, 4, 890, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1266 = DIVU_MMR6
6082 { 1267, 3, 1, 4, 891, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1267 = DIV_MMR6
6110 { 1295, 3, 1, 4, 1201, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, ImplicitList11, OperandInfo62, -1 ,nullptr }, // Inst #1295 = DMUL
6182 { 1367, 3, 1, 4, 830, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1367 = DSUB
6183 { 1368, 3, 1, 4, 831, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1368 = DSUBu
6554 { 1739, 2, 1, 2, 740, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1739 = LI16_MM
6555 { 1740, 2, 1, 2, 781, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1740 = LI16_MMR6
6569 { 1754, 2, 1, 4, 783, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1754 = LUI_MMR6
6573 { 1758, 2, 1, 4, 360, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1758 = LUi
6574 { 1759, 2, 1, 4, 833, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1759 = LUi64
6575 { 1760, 2, 1, 4, 741, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1760 = LUi_MM
6752 { 1937, 3, 1, 4, 888, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1937 = MODU_MMR6
6753 { 1938, 3, 1, 4, 889, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1938 = MOD_MMR6
6762 { 1947, 2, 1, 2, 742, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #1947 = MOVE16_MM
6763 { 1948, 2, 1, 2, 784, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #1948 = MOVE16_MMR6
6764 { 1949, 4, 2, 2, 743, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #1949 = MOVEP_MM
6765 { 1950, 4, 2, 2, 1549, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #1950 = MOVEP_MMR6
6872 { 2057, 3, 1, 4, 884, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2057 = MUHU_MMR6
6873 { 2058, 3, 1, 4, 885, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2058 = MUH_MMR6
6874 { 2059, 3, 1, 4, 481, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, ImplicitList6, OperandInfo63, -1 ,nullptr }, // Inst #2059 = MUL
6906 { 2091, 3, 1, 4, 886, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2091 = MULU_MMR6
6911 { 2096, 3, 1, 4, 876, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, ImplicitList6, OperandInfo63, -1 ,nullptr }, // Inst #2096 = MUL_MM
6912 { 2097, 3, 1, 4, 887, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2097 = MUL_MMR6
6952 { 2137, 3, 1, 4, 362, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2137 = OR
6955 { 2140, 3, 1, 4, 835, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #2140 = OR64
6957 { 2142, 3, 1, 4, 788, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #2142 = ORI_MMR6
6958 { 2143, 3, 1, 4, 746, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2143 = OR_MM
6959 { 2144, 3, 1, 4, 787, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2144 = OR_MMR6
6961 { 2146, 3, 1, 4, 495, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #2146 = ORi
6962 { 2147, 3, 1, 4, 801, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #2147 = ORi64
6963 { 2148, 3, 1, 4, 747, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #2148 = ORi_MM
6964 { 2149, 3, 1, 2, 727, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #2149 = OrRxRxRy16
7312 { 2497, 3, 1, 4, 364, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2497 = SUB
7349 { 2534, 3, 1, 4, 793, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2534 = SUBU_MMR6
7366 { 2551, 3, 1, 4, 762, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2551 = SUB_MM
7367 { 2552, 3, 1, 4, 794, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2552 = SUB_MMR6
7368 { 2553, 3, 1, 4, 365, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2553 = SUBu
7369 { 2554, 3, 1, 4, 761, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2554 = SUBu_MM
7433 { 2618, 3, 1, 2, 727, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #2618 = SubuRxRyRz16
7497 { 2682, 3, 1, 4, 1200, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList33, OperandInfo62, -1 ,nullptr }, // Inst #2682 = V3MULU
7498 { 2683, 3, 1, 4, 1200, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList25, OperandInfo62, -1 ,nullptr }, // Inst #2683 = VMM0
7499 { 2684, 3, 1, 4, 1200, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList34, OperandInfo62, -1 ,nullptr }, // Inst #2684 = VMULU
7513 { 2698, 3, 1, 4, 366, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2698 = XOR
7516 { 2701, 3, 1, 4, 807, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #2701 = XOR64
7518 { 2703, 3, 1, 4, 797, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #2703 = XORI_MMR6
7519 { 2704, 3, 1, 4, 764, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2704 = XOR_MM
7520 { 2705, 3, 1, 4, 796, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2705 = XOR_MMR6
7522 { 2707, 3, 1, 4, 503, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #2707 = XORi
7523 { 2708, 3, 1, 4, 807, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #2708 = XORi64
7524 { 2709, 3, 1, 4, 765, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #2709 = XORi_MM
7525 { 2710, 3, 1, 2, 727, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #2710 = XorRxRxRy16
gen/lib/Target/NVPTX/NVPTXGenInstrInfo.inc 6641 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
6654 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
gen/lib/Target/PowerPC/PPCGenInstrInfo.inc 2918 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
2931 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
3187 { 279, 3, 1, 4, 117, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #279 = ADDIStocHA8
3198 { 290, 3, 1, 4, 117, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #290 = ADDItocL
3420 { 512, 1, 1, 4, 129, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #512 = CRSET
3421 { 513, 1, 1, 4, 129, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #513 = CRUNSET
3945 { 1037, 2, 1, 4, 116, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x8ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1037 = LI
3946 { 1038, 2, 1, 4, 116, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x8ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1038 = LI8
3947 { 1039, 2, 1, 4, 116, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x8ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1039 = LIS
3948 { 1040, 2, 1, 4, 116, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x8ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1040 = LIS8
4234 { 1326, 2, 1, 4, 68, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, ImplicitList2, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1326 = QVGPCI
4853 { 1945, 1, 1, 4, 98, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1945 = V_SET0
4854 { 1946, 1, 1, 4, 98, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1946 = V_SET0B
4855 { 1947, 1, 1, 4, 98, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1947 = V_SET0H
4856 { 1948, 1, 1, 4, 162, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1948 = V_SETALLONES
4857 { 1949, 1, 1, 4, 162, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1949 = V_SETALLONESB
4858 { 1950, 1, 1, 4, 162, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1950 = V_SETALLONESH
5093 { 2185, 1, 1, 4, 97, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr }, // Inst #2185 = XXLEQVOnes
5100 { 2192, 1, 1, 4, 97, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #2192 = XXLXORdpz
5101 { 2193, 1, 1, 4, 97, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #2193 = XXLXORspz
5102 { 2194, 1, 1, 4, 97, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr }, // Inst #2194 = XXLXORz
gen/lib/Target/RISCV/RISCVGenInstrInfo.inc 672 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
685 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
887 { 225, 3, 1, 4, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x3ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #225 = ADDI
1118 { 456, 2, 1, 4, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #456 = LUI
1128 { 466, 3, 1, 4, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x3ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #466 = ORI
1169 { 507, 3, 1, 4, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x3ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #507 = XORI
gen/lib/Target/Sparc/SparcGenInstrInfo.inc 940 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
953 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
gen/lib/Target/SystemZ/SystemZGenInstrInfo.inc 4330 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
4343 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
4629 { 309, 2, 1, 0, 96, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #309 = IIFMux
4642 { 322, 2, 1, 0, 40, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #322 = LHIMux
5547 { 1227, 2, 1, 6, 97, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #1227 = IIHF
5550 { 1230, 2, 1, 6, 100, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1230 = IILF
5646 { 1326, 4, 1, 4, 86, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x8ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #1326 = LA
5659 { 1339, 2, 1, 6, 86, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1339 = LARL
5664 { 1344, 4, 1, 6, 86, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0xcULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #1344 = LAY
5718 { 1398, 2, 1, 6, 39, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1398 = LGFI
5723 { 1403, 2, 1, 4, 39, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1403 = LGHI
5731 { 1411, 2, 1, 4, 40, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1411 = LHI
5755 { 1435, 2, 1, 6, 37, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1435 = LLIHF
5756 { 1436, 2, 1, 4, 37, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1436 = LLIHH
5757 { 1437, 2, 1, 4, 37, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1437 = LLIHL
5758 { 1438, 2, 1, 6, 38, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1438 = LLILF
5759 { 1439, 2, 1, 4, 38, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1439 = LLILH
5760 { 1440, 2, 1, 4, 38, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1440 = LLILL
6857 { 2537, 2, 1, 6, 525, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo346, -1 ,nullptr }, // Inst #2537 = VGBM
6870 { 2550, 4, 1, 6, 526, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo348, -1 ,nullptr }, // Inst #2550 = VGM
6871 { 2551, 3, 1, 6, 526, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo349, -1 ,nullptr }, // Inst #2551 = VGMB
6872 { 2552, 3, 1, 6, 526, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo349, -1 ,nullptr }, // Inst #2552 = VGMF
6873 { 2553, 3, 1, 6, 526, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo349, -1 ,nullptr }, // Inst #2553 = VGMG
6874 { 2554, 3, 1, 6, 526, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo349, -1 ,nullptr }, // Inst #2554 = VGMH
7054 { 2734, 1, 1, 6, 524, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo364, -1 ,nullptr }, // Inst #2734 = VONE
7087 { 2767, 3, 1, 6, 527, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo349, -1 ,nullptr }, // Inst #2767 = VREPI
7088 { 2768, 2, 1, 6, 527, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo346, -1 ,nullptr }, // Inst #2768 = VREPIB
7089 { 2769, 2, 1, 6, 527, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo346, -1 ,nullptr }, // Inst #2769 = VREPIF
7090 { 2770, 2, 1, 6, 527, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo346, -1 ,nullptr }, // Inst #2770 = VREPIG
7091 { 2771, 2, 1, 6, 527, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo346, -1 ,nullptr }, // Inst #2771 = VREPIH
7200 { 2880, 1, 1, 6, 523, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo364, -1 ,nullptr }, // Inst #2880 = VZERO
gen/lib/Target/WebAssembly/WebAssemblyGenInstrInfo.inc 1565 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
1578 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
2053 { 498, 2, 1, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo89, -1 ,nullptr }, // Inst #498 = CONST_F32
2054 { 499, 1, 0, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo90, -1 ,nullptr }, // Inst #499 = CONST_F32_S
2055 { 500, 2, 1, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #500 = CONST_F64
2056 { 501, 1, 0, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo92, -1 ,nullptr }, // Inst #501 = CONST_F64_S
2057 { 502, 2, 1, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo93, -1 ,nullptr }, // Inst #502 = CONST_I32
2058 { 503, 1, 0, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo94, -1 ,nullptr }, // Inst #503 = CONST_I32_S
2059 { 504, 2, 1, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo95, -1 ,nullptr }, // Inst #504 = CONST_I64
2060 { 505, 1, 0, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo96, -1 ,nullptr }, // Inst #505 = CONST_I64_S
2061 { 506, 17, 1, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo97, -1 ,nullptr }, // Inst #506 = CONST_V128_v16i8
2062 { 507, 16, 0, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo98, -1 ,nullptr }, // Inst #507 = CONST_V128_v16i8_S
2063 { 508, 3, 1, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo99, -1 ,nullptr }, // Inst #508 = CONST_V128_v2f64
2064 { 509, 2, 0, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo100, -1 ,nullptr }, // Inst #509 = CONST_V128_v2f64_S
2065 { 510, 3, 1, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo101, -1 ,nullptr }, // Inst #510 = CONST_V128_v2i64
2066 { 511, 2, 0, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo102, -1 ,nullptr }, // Inst #511 = CONST_V128_v2i64_S
2067 { 512, 5, 1, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo103, -1 ,nullptr }, // Inst #512 = CONST_V128_v4f32
2068 { 513, 4, 0, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo104, -1 ,nullptr }, // Inst #513 = CONST_V128_v4f32_S
2069 { 514, 5, 1, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo105, -1 ,nullptr }, // Inst #514 = CONST_V128_v4i32
2070 { 515, 4, 0, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo106, -1 ,nullptr }, // Inst #515 = CONST_V128_v4i32_S
2071 { 516, 9, 1, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo107, -1 ,nullptr }, // Inst #516 = CONST_V128_v8i16
2072 { 517, 8, 0, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo108, -1 ,nullptr }, // Inst #517 = CONST_V128_v8i16_S
gen/lib/Target/X86/X86GenInstrInfo.inc17698 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
17711 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
17873 { 185, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #185 = AVX1_SETALLONES
17874 { 186, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #186 = AVX2_SETALLONES
17875 { 187, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #187 = AVX512_128_SET0
17876 { 188, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #188 = AVX512_256_SET0
17877 { 189, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #189 = AVX512_512_SET0
17878 { 190, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #190 = AVX512_512_SETALLONES
17881 { 193, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #193 = AVX512_FsFLD0F128
17882 { 194, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #194 = AVX512_FsFLD0SD
17883 { 195, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #195 = AVX512_FsFLD0SS
17884 { 196, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #196 = AVX_SET0
17885 { 197, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #197 = FsFLD0F128
17886 { 198, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #198 = FsFLD0SD
17887 { 199, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #199 = FsFLD0SS
17888 { 200, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #200 = KSET0D
17889 { 201, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #201 = KSET0Q
17890 { 202, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #202 = KSET0W
17891 { 203, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #203 = KSET1D
17892 { 204, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #204 = KSET1Q
17893 { 205, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #205 = KSET1W
17896 { 208, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #208 = MMX_SET0
17899 { 211, 2, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #211 = MOV32ImmSExti8
17900 { 212, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, ImplicitList1, OperandInfo62, -1 ,nullptr }, // Inst #212 = MOV32r0
17901 { 213, 1, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, ImplicitList1, OperandInfo62, -1 ,nullptr }, // Inst #213 = MOV32r1
17902 { 214, 1, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, ImplicitList1, OperandInfo62, -1 ,nullptr }, // Inst #214 = MOV32r_1
17903 { 215, 2, 1, 0, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #215 = MOV32ri64
17904 { 216, 2, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #216 = MOV64ImmSExti8
17927 { 239, 6, 1, 0, 1159, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #239 = VMOVAPSZ128rm_NOVLX
17929 { 241, 6, 1, 0, 1185, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #241 = VMOVAPSZ256rm_NOVLX
17931 { 243, 6, 1, 0, 1159, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #243 = VMOVUPSZ128rm_NOVLX
17933 { 245, 6, 1, 0, 1185, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #245 = VMOVUPSZ256rm_NOVLX
17934 { 246, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #246 = V_SET0
17935 { 247, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #247 = V_SETALLONES
18961 { 1273, 6, 1, 0, 1053, 0|(1ULL<<MCID::Rematerializable), 0x2340000121ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #1273 = LEA32r
18963 { 1275, 6, 1, 0, 1053, 0|(1ULL<<MCID::Rematerializable), 0x2340010021ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1275 = LEA64r
19340 { 1652, 2, 1, 0, 6, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2e00080082ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #1652 = MOV16ri
19342 { 1654, 6, 1, 0, 938, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x22c00000a1ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr }, // Inst #1654 = MOV16rm
19360 { 1672, 2, 1, 0, 6, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2e000c0102ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #1672 = MOV32ri
19362 { 1674, 6, 1, 0, 62, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x22c0000121ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #1674 = MOV32rm
19377 { 1689, 2, 1, 0, 6, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x2e00130002ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1689 = MOV64ri
19378 { 1690, 2, 1, 0, 6, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x31c0110038ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1690 = MOV64ri32
19379 { 1691, 6, 1, 0, 62, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x22c0010021ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1691 = MOV64rm
19396 { 1708, 2, 1, 0, 6, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2c00020002ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #1708 = MOV8ri
19398 { 1710, 6, 1, 0, 62, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x2280000021ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #1710 = MOV8rm
19399 { 1711, 6, 1, 0, 62, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x2280000021ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #1711 = MOV8rm_NOREX
19404 { 1716, 6, 1, 0, 11, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0xa08002821ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #1716 = MOVAPDrm
19408 { 1720, 6, 1, 0, 11, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0xa04002021ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #1720 = MOVAPSrm
19428 { 1740, 6, 1, 0, 177, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x1bcc002821ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #1740 = MOVDQArm
19432 { 1744, 6, 1, 0, 624, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x1bcc003021ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #1744 = MOVDQUrm
19465 { 1777, 6, 1, 0, 747, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x408003821ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #1777 = MOVSDrm
19466 { 1778, 6, 1, 0, 747, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x408003821ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #1778 = MOVSDrm_alt
19478 { 1790, 6, 1, 0, 747, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x404003021ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #1790 = MOVSSrm
19479 { 1791, 6, 1, 0, 747, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x404003021ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1791 = MOVSSrm_alt
19504 { 1816, 6, 1, 0, 625, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x408002821ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #1816 = MOVUPDrm
19508 { 1820, 6, 1, 0, 625, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x404002021ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #1820 = MOVUPSrm
25264 { 7576, 6, 1, 0, 13, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x10a18002821ULL, nullptr, nullptr, OperandInfo413, -1 ,nullptr }, // Inst #7576 = VMOVAPDYrm
25269 { 7581, 6, 1, 0, 1159, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x2004a38002821ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #7581 = VMOVAPDZ128rm
25280 { 7592, 6, 1, 0, 1185, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x4014a38002821ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #7592 = VMOVAPDZ256rm
25291 { 7603, 6, 1, 0, 1185, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x8084a38002821ULL, nullptr, nullptr, OperandInfo419, -1 ,nullptr }, // Inst #7603 = VMOVAPDZrm
25301 { 7613, 6, 1, 0, 11, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0xa18002821ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #7613 = VMOVAPDrm
25305 { 7617, 6, 1, 0, 13, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x10a14002021ULL, nullptr, nullptr, OperandInfo413, -1 ,nullptr }, // Inst #7617 = VMOVAPSYrm
25310 { 7622, 6, 1, 0, 1159, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x2000a34002021ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #7622 = VMOVAPSZ128rm
25321 { 7633, 6, 1, 0, 1185, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x4010a34002021ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #7633 = VMOVAPSZ256rm
25332 { 7644, 6, 1, 0, 1185, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x8080a34002021ULL, nullptr, nullptr, OperandInfo419, -1 ,nullptr }, // Inst #7644 = VMOVAPSZrm
25342 { 7654, 6, 1, 0, 11, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0xa14002021ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #7654 = VMOVAPSrm
25375 { 7687, 6, 1, 0, 1161, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x2001bfc002821ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #7687 = VMOVDQA32Z128rm
25386 { 7698, 6, 1, 0, 1188, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x4011bfc002821ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #7698 = VMOVDQA32Z256rm
25397 { 7709, 6, 1, 0, 1188, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x8081bfc002821ULL, nullptr, nullptr, OperandInfo419, -1 ,nullptr }, // Inst #7709 = VMOVDQA32Zrm
25408 { 7720, 6, 1, 0, 1161, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x2005bfc002821ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #7720 = VMOVDQA64Z128rm
25419 { 7731, 6, 1, 0, 1188, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x4015bfc002821ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #7731 = VMOVDQA64Z256rm
25430 { 7742, 6, 1, 0, 1188, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x8085bfc002821ULL, nullptr, nullptr, OperandInfo419, -1 ,nullptr }, // Inst #7742 = VMOVDQA64Zrm
25440 { 7752, 6, 1, 0, 447, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x11bdc002821ULL, nullptr, nullptr, OperandInfo413, -1 ,nullptr }, // Inst #7752 = VMOVDQAYrm
25444 { 7756, 6, 1, 0, 177, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x1bdc002821ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #7756 = VMOVDQArm
25449 { 7761, 6, 1, 0, 1161, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x2005bfc003821ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #7761 = VMOVDQU16Z128rm
25460 { 7772, 6, 1, 0, 1188, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x4015bfc003821ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #7772 = VMOVDQU16Z256rm
25471 { 7783, 6, 1, 0, 1188, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x8085bfc003821ULL, nullptr, nullptr, OperandInfo419, -1 ,nullptr }, // Inst #7783 = VMOVDQU16Zrm
25482 { 7794, 6, 1, 0, 1161, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x2001bfc003021ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #7794 = VMOVDQU32Z128rm
25493 { 7805, 6, 1, 0, 1188, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x4011bfc003021ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #7805 = VMOVDQU32Z256rm
25504 { 7816, 6, 1, 0, 1188, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x8081bfc003021ULL, nullptr, nullptr, OperandInfo419, -1 ,nullptr }, // Inst #7816 = VMOVDQU32Zrm
25515 { 7827, 6, 1, 0, 1161, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x2005bfc003021ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #7827 = VMOVDQU64Z128rm
25526 { 7838, 6, 1, 0, 1188, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x4015bfc003021ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #7838 = VMOVDQU64Z256rm
25537 { 7849, 6, 1, 0, 1188, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x8085bfc003021ULL, nullptr, nullptr, OperandInfo419, -1 ,nullptr }, // Inst #7849 = VMOVDQU64Zrm
25548 { 7860, 6, 1, 0, 1161, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x2001bfc003821ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #7860 = VMOVDQU8Z128rm
25559 { 7871, 6, 1, 0, 1188, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x4011bfc003821ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #7871 = VMOVDQU8Z256rm
25570 { 7882, 6, 1, 0, 1188, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x8081bfc003821ULL, nullptr, nullptr, OperandInfo419, -1 ,nullptr }, // Inst #7882 = VMOVDQU8Zrm
25580 { 7892, 6, 1, 0, 447, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x11bdc003021ULL, nullptr, nullptr, OperandInfo413, -1 ,nullptr }, // Inst #7892 = VMOVDQUYrm
25584 { 7896, 6, 1, 0, 177, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x1bdc003021ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #7896 = VMOVDQUrm
25647 { 7959, 6, 1, 0, 1142, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x1004438003821ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #7959 = VMOVSDZrm
25648 { 7960, 6, 1, 0, 1142, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x1004438003821ULL, nullptr, nullptr, OperandInfo473, -1 ,nullptr }, // Inst #7960 = VMOVSDZrm_alt
25658 { 7970, 6, 1, 0, 747, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x418003821ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #7970 = VMOVSDrm
25659 { 7971, 6, 1, 0, 747, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x418003821ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #7971 = VMOVSDrm_alt
25712 { 8024, 6, 1, 0, 1142, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x800434003021ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #8024 = VMOVSSZrm
25713 { 8025, 6, 1, 0, 1142, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x800434003021ULL, nullptr, nullptr, OperandInfo475, -1 ,nullptr }, // Inst #8025 = VMOVSSZrm_alt
25723 { 8035, 6, 1, 0, 747, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x414003021ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #8035 = VMOVSSrm
25724 { 8036, 6, 1, 0, 747, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x414003021ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #8036 = VMOVSSrm_alt
25728 { 8040, 6, 1, 0, 13, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x10418002821ULL, nullptr, nullptr, OperandInfo413, -1 ,nullptr }, // Inst #8040 = VMOVUPDYrm
25733 { 8045, 6, 1, 0, 1159, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x2004438002821ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #8045 = VMOVUPDZ128rm
25744 { 8056, 6, 1, 0, 1185, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x4014438002821ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #8056 = VMOVUPDZ256rm
25755 { 8067, 6, 1, 0, 1185, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x8084438002821ULL, nullptr, nullptr, OperandInfo419, -1 ,nullptr }, // Inst #8067 = VMOVUPDZrm
25765 { 8077, 6, 1, 0, 11, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x418002821ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #8077 = VMOVUPDrm
25769 { 8081, 6, 1, 0, 13, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x10414002021ULL, nullptr, nullptr, OperandInfo413, -1 ,nullptr }, // Inst #8081 = VMOVUPSYrm
25774 { 8086, 6, 1, 0, 1159, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x2000434002021ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #8086 = VMOVUPSZ128rm
25785 { 8097, 6, 1, 0, 1185, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x4010434002021ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #8097 = VMOVUPSZ256rm
25796 { 8108, 6, 1, 0, 1185, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x8080434002021ULL, nullptr, nullptr, OperandInfo419, -1 ,nullptr }, // Inst #8108 = VMOVUPSZrm
25806 { 8118, 6, 1, 0, 11, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x414002021ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #8118 = VMOVUPSrm
gen/lib/Target/XCore/XCoreGenInstrInfo.inc 509 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
522 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
678 { 179, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #179 = FRAME_TO_ARGS_OFFSET
786 { 287, 1, 0, 4, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #287 = LDAPB_lu10
787 { 288, 1, 0, 2, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #288 = LDAPB_u10
788 { 289, 1, 0, 4, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #289 = LDAPF_lu10
789 { 290, 1, 0, 4, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #290 = LDAPF_lu10_ba
790 { 291, 1, 0, 2, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #291 = LDAPF_u10
793 { 294, 1, 0, 4, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo3, -1 ,nullptr }, // Inst #294 = LDAWCP_lu6
794 { 295, 1, 0, 2, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo3, -1 ,nullptr }, // Inst #295 = LDAWCP_u6
795 { 296, 2, 1, 4, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #296 = LDAWDP_lru6
796 { 297, 2, 1, 2, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #297 = LDAWDP_ru6
801 { 302, 2, 1, 4, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #302 = LDC_lru6
802 { 303, 2, 1, 2, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #303 = LDC_ru6
808 { 309, 2, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #309 = LDWCP_lru6
809 { 310, 1, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo3, -1 ,nullptr }, // Inst #310 = LDWCP_lu10
810 { 311, 2, 1, 2, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #311 = LDWCP_ru6
811 { 312, 1, 0, 2, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo3, -1 ,nullptr }, // Inst #312 = LDWCP_u10
826 { 327, 2, 1, 2, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #327 = MKMSK_rus
include/llvm/CodeGen/MachineInstr.h 957 return hasProperty(MCID::Rematerializable, Type);
include/llvm/MC/MCInstrDesc.h 506 return Flags & (1ULL << MCID::Rematerializable);